Engenharia Elétrica
URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/21
Navegar
56 resultados
Resultados da Pesquisa
Artigo de evento 0 Citação(ões) na Scopus Implementation of high performance operational transconductance amplifiers using graded-channel SOI nMOSFETs(2005-05-20) Salvador Gimenez; Marcelo Antonio Pavanello; Joao Antonio Martino; FLANDRE, D.This paper presents the performance of operational transconductance amplifiers (OTAs) fabricated with Graded-Channel (GC) SOI nMOSFETs at room temperature. Different design targets were taken in account such as similar power dissipation, transconductance over drain current ratio and die area. Comparisons with high voltage gain and high unit voltage gain frequency OTAs made with conventional SOI nMOSFETs are performed showing that the GC OTAs present larger open-loop voltage gain without degrading unit voltage gain frequency, the phase margin, and slew rate with a significant required die area reduction depending on used LLD/L ratio. Experimental results and SPICE simulations are used to validate the analysis.Artigo de evento 9 Citação(ões) na Scopus Early voltage behavior in circular gate SOI nMOSFET using 0.13 μm partially-depleted SOI CMOS technology(2006-09-01) Salvador Gimenez; FERREIRA, R. M. G.; Joao Antonio MartinoThis paper studies the Early voltage behavior in circular gate partially-depleted SOI nMOSFET. The drain/source asymmetric effects are considered in terms of drain current as a function of the gate and drain voltages. Drain current comparisons with rectangular gate partially-depleted SOI nMOSFET are performed, regarding the same effective channel length and width. Experimental results and three-dimensional simulations are used to qualify the results. © 2006 The Electrochemical Society.Artigo 0 Citação(ões) na Scopus Boosting the MOSFETs matching by using diamond layout style(2017-04-05) PERUZZI, V. V.; RENAUX, C.; FLANDRE, D.; Salvador Gimenez© 2017, Brazilian Microelectronics Society. All rights reserved.This manuscript presents an experimental comparative study between the Metal-Oxide-Semiconductor (MOS) Silicon-On-Insulator (SOI) Field Effect Transistors, n-type, (nMOSFETs) matching, which are implemented with the hexagonal gate shape (Diamond) and standard rectangular ones. The main analog parameters and figures of merit of 360 devices are investigated. The results establish that the Diamond SOI MOSFETs with α angles equal to 90o can boost in more than in average -45.8% with a standard deviation of 20.1% the devices matching in comparison to those found with the typical rectangular SOI MOSFETs, concerning the same gate area and bias conditions. Consequently, the Diamond layout style is an alternative technique to reduce the nMOSFETs’ mismatching, considering the analog SOI Complementary MOS (CMOS) integrated circuits (ICs) applications.- Impact in the Parallel Processing of IHM-Plasma Using the Earliest-Deadline-First Algorithm for the Task-Scheduler Realized by Hardware(2023-05-05) KRAUSE, I.; DANTA, L. P.; Salvador Gimenez© 2023, Brazilian Microelectronics Society. All rights reserved.This work studies the impact in the parallel processing of the Interlocked-Hardware-Microkernel (IHM) Plasma microprocessor (IHM-Plasma) by implementing the Earliest-Deadline-First (EDF) algorithm by hardware in the task-scheduler block that belongs to those task-based operational systems, such as that related to the real-time operational systems (RTOS). IHM-Plasma presents Reduced Instruction Set Computer (RISC) architecture. Results show that the EDF algorithm running in IHM-Plasma's hardware has increased the number of tasks executed per second by up to 174% compared to the same algorithm running in software. The developed work has great potential use in Hard Real-Time Systems and others where a rigid control of deadlines is essential and hold many tasks.
- The Second Generation of Layout Styles to Further Boost the Electrical Performance of Analog MOSFETs(2022-09-17) SILVA, G. A. DA; Salvador Gimenez© 2022, Brazilian Microelectronics Society. All rights reserved.Previous studies have shown that the first generation of layout styles composed by the Diamond (hexagonal), Octo (octagonal), and Ellipsoidal gate shapes for the imple-menting of the planar and three-dimensional Metal-Oxide-Semiconductor (MOS) Field Effect Transistors (MOSFETs) are capable of boosting their analog and digital electrical per-formances, ionizing radiation tolerances, and reducing the die areas used in comparison to those transistors designed with conventional rectangular layout styles. In order to further boost these features obtained by the use of the first generation of layout styles, one of elements of the second generation of layout styles for MOSFETs, entitled Half-Diamond, is being intro-duced. This new proposal is an evolution of the Diamond layout style, which is able to preserve the Longitudinal Corner Effect (LCE), the Parallel Connection of MOSFETs with Different Channel Lengths Effect (PAMDLE), and the Deactivation of Parasitic MOSFETs in Bird’s Beaks Regions (DEMPAMBBRE) effects promoted by the first generation. This layout style can also reduce the effective channel lengths of MOSFETs in comparison to those reached by the Diamond layout style. In this context, this work performs an experimental comparative study between the electric performances of MOSFETs implemented with the Half-Diamond, Diamond, and Conventional layout styles, considering they present the same gate areas, bias conditions, and the 180 nm Bulk CMOS ICs technology node. The experimental results show that the satu-ration drain current normalized by the aspect ratio and low-frequency open-loop voltage gain, in dB, of MOSFET implemented with the Half-Diamond layout style (HDM) are 17% and 3.5% higher, respectively, than those found in MOSFETs counterparts, designed with the conventional rectangular gate shape (CMs).
- Customized Imperialist Competitive Algorithm Methodology to Optimize Robust Miller CMOS OTAs(2022) GALEMBECK, E. H. S.; Salvador Gimenez; MORETO, R. A. D. L.© 2022 by the authors.The design and optimization of the analog complementary metal-oxide-semiconductor (CMOS) integrated circuits (ICs) are intrinsically complicated and depend heavily on the designer’s experience, and are associated with very long design and optimization-cycle times. In addition, in order to the analog and radiofrequency (RF) CMOS IC work suitably in practice, it is necessary to perform robustness analyses (RAs) through Simulation Program with Integrated Circuit Emphasis (SPICE) simulations, which result in still-higher design and optimization cycle times and therefore represent the biggest bottleneck to the launching of new electronic products. In this context, this manuscript aims to present, for the first time, the use of a custom imperialist competitive algorithm (ICA) in order to reduce the design and optimization-cycle times of analog CMOS ICs. In this study, we implement some Miller CMOS operational transconductance amplifiers (OTAs) using the computational tool named iMTGSPICE, considering two different bulk CMOS IC manufacturing processes from Taiwan Semiconductor Company (TSMC) (180 nm and 65 nm nodes) and two evolutionary optimization methodologies of artificial intelligence, i.e., ICA and a genetic algorithm (GA). The main result obtained by this work shows that, by using an ICA-customized evolutionary algorithm to perform the design and optimization processes of Miller CMOS OTAs, it is possible to reduce the design and optimization-cycle times by up to 83% in relation to those implemented with the GA-customized evolutionary algorithm, achieving practically the same electrical performance.
- Impact of Temperature Effects in the Zero Temperature Coefficient of the Ellipsoidal MOSFET(2022-08-22) DE LIMA, M. P. B.; PEIXOTO, M. A. P.; CORREIA, M. M.; GALEMBECK, E. H. S.; Salvador Gimenez; CAMILO, L. M.© 2022 IEEE.The zero temperature coefficient (ZTC) is investigated by the simple model and three-dimensional numerical simulations in the Metal-Oxide-Semiconductor (MOS) Field Effect Transistor (MOSFET) with the ellipsoidal (EM) and conventional rectangular gate geometries (CM), considering the same channel widths (W), gate areas (AG) and bias condition (BC) technology. A simple model is used to study the behavior of the gate voltage at ZTC (VZTC) in the linear and the saturation region. The influence of the temperature mobility degradation on VZTC is analyzed for EM and CM devices. The VZTC changes in the temperature range investigated showed a temperature mobility degradation dependence and the both devices showed the same behavior. The analysis takes into account temperature dependence model parameters such as threshold voltage and mobility. The analytical predictions are in very close agreement with 3D simulations results in spite of the simplification used for the VZTC model as a function of temperature in the linear and the saturation region.
- Impact of using Octogonal Layout Style in Planar Power MOSFETs(2022-08-22) DA SILVA, G. A.; Salvador Gimenez© 2022 IEEE.Previous studies have already shown that the use of alternative gate shapes for planar and tridimensional MOSFETs are capable of boosting their analog and digital electrical performances and their ionizing radiations robustness. In this scenario, this work has the objective to study the impact of the use of octagonal layout style (OCTO), as the basic cell, to the implementing of the Planar Power MOSFET (PPM). The main results of this paper show that the PPM layouted with OCTO layout styles, as the basic cells, are able to improve the drain saturation current (IDS-sat) about 668%%, in relation to that implemented with conventional rectangular layout style, considering that they present the same gate area and bias conditions. Therefore, this type of layout approach can be considered an alternative layout to improve the electrical performance of PPMs.
- Applying the diamond layout style for FinFET(2012-12-02) NETO, E. D.; Salvador GimenezThe FinFET devices have been on focus in recent years due its elevated gate control capability over the channel region, what gives this technology a scalability advantage against others. The planar Diamond MOSFET layout, on the other hand, has also shown great results regarding its possible use on integrated circuits applications. In this paper, the concept of the Diamond layout style is extended to its three-dimensional version, the Diamond FinFET. 3D numerical simulations are performed in order to compare the possible advantages and disadvantages between this innovative layout style and its conventional counterpart, keeping the same gate area, geometric factor and bias conditions. It is shown that this new device inherits the qualities of its planar MOSFET version and it is proved that it can reduce significantly the die area of the analog and digital (mixed) low-power low-voltage integrated circuits due to its high capability as current driver. © The Electrochemical Society.
- New Hybrid Generation of Layout Styles to Boost the Electrical, Energy, and Frequency Response Performances of Analog MOSFETs(2022-01-05) GALEMBECK, E. H. S.; Salvador GimenezIEEEIt is known that the hexagonal (Diamond) layout style is capable of boosting the electrical performance and ionizing radiation tolerances of metal-oxide-semiconductor field-effect-transistors (MOSFETs). In order to further improve the figures of merit of these devices, it was proposed a hybrid gate geometry that is an evolution of the hexagonal layout style, entitled Half-Diamond. This innovative layout style is able to generate the same electrical effects that the Diamond is able to generate, and it is innovative because it is capable of further reducing the effective channel lengths of MOSFETs implemented with Diamond and rectangular layout styles. Thus, this work describes a comparative study by 3-D numerical simulations data and experimental data between the MOSFETs implemented with the Half-Diamond and Conventional layout styles. The main results found have indicated that the saturation drain current and transconductance of MOSFET layouted with Half-Diamond are 36% and 27% higher, respectively, than those measured in the Conventional MOSFET. Other results have shown that the innovative half-diamond layout style (HDLS) for MOSFETs is capable of reducing the dissipated electrical power in approximately 62% and, therefore, it is an alternative hardness-by-design strategy to remarkably improve complementary metal-oxide-semiconductor (CMOS) integrated circuits (ICs) energy efficiency. Besides, the electrical behaviors of longitudinal corner effect (LCE), parallel connection of MOSFETs with different channel lengths effect (PAMDLE), and deactivation of parasitic MOSFETs in the bird's beak regions effect (DEPAMBBRE) of the MOSFETs implemented with the HDLS are studied in detail to justify the results found.