Engenharia Elétrica
URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/21
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22 resultados
Resultados da Pesquisa
- Junctionless nanowire transistors effective channel length extraction through capacitance characteristics(2023-10-05) SILVA, E. M.; TREVISOLI, R.; Rodrigo Doria© 2023 Elsevier LtdThis work aims to extract the effective channel length (LEFF) of Junctionless Nanowire Transistors (JNT) through the maximum gate capacitance of the devices. The LEFF extraction has been done by extrapolating the maximum gate capacitance as a function of the devices’ channel length (LMASK) and has shown that LEFF is around 10–15 nm longer than LMASK for devices of different channel doping concentrations.
- Junctionless Nanowire Transistor for Analog Applications: Cascode Current Mirror Configuration(2022-08-05) SHIBUTANI, A. B.; TREVISOLI, R.; Rodrigo Doria© 2022 IEEE.In this paper, a cascode current mirror compounded by junctionless nanowire transistors is analyzed for the first time. Thus, the performance and the mirroring precision of the configuration were investigated considering the internal circuit feedback and the high output resistance. On this basis, symmetrical and asymmetrical configurations were examined to comprehend the junctionless nanowire transistor behavior as a current source.
- Variability Modeling in Triple-Gate Junctionless Nanowire Transistors(2022-01-05) TREVISOLI, R.; Marcelo Antonio Pavanello; Rodrigo Doria; CAPOVILLA, C.E.; BARRAUD, S.; Michelly De SouzaIEEEThis work aims at proposing an analytical model for the variability of the threshold voltage and drain current in junctionless nanowire transistors. The model is continuous in all operation regions and has been validated through Monte Carlo simulations using a physically based drain current model and 3-D numerical simulations. A discussion about the influences of each variability source based on the proposed model is carried out. Finally, the modeled results are compared to the experimental data for a fully physical validation.
- NBTI Dependence on Temperature in Junctionless Nanowire Transistors(2021-07-27) GRAZIANO, N.; TREVISOLI, R.; Rodrigo, Doria©2021 IEEE.This paper discusses the nature of degradation by NBTI effect in pMOS junctionless devices when varying the temperature. The results were obtained through simulations validated to experimental data. Devices with different dimensions and doping, have been subjected to a temperature range that varies between 270 and 380 K. The simulations were performed for different values of VGT and as a result it is possible to observe that when increasing temperature up to 340 K, the threshold voltage variation due to NBTI is also increased. However, for larger temperatures the NBTI effect seems to stabilize or even reduce.
- Interface traps density extraction through transient measurements in junctionless transistors(2022-08-05) TEICEIRA DA FONTE, E.; TREVISOLI, R.; BARRAUD S.; Rodrigo Doria© 2022 Elsevier LtdThis paper presents an extraction method for the interface traps density on Junctionless Transistors (JNTs) using an adapted charge pumping technique. To the best of our knowledge, this is the first work to apply this method in JNTs. Initially, it was stated through numerical simulations that a transient current, which increases with the trap density, is observed in the devices when the charge pumping method is applied. Then, a measurement setup was proposed to extract the pumping current resultant from a gate pulse and a mathematical expression was proposed to extract the density of trapped charges in the Oxide/Silicon interface (Nit). Aiming to demonstrate the method applicability for determining the JNTs interface quality, it was applied to simulations considering different trap densities as well as to experimental data of Junctionless Nanowire Transistors. It was observed that the method accuracy increases for larger trap densities and presents agreement to theoretical data for Nit > 1 × 1011 cm−2.
- Junctionless Nanowire Transistors Based Common-Source Current Mirror(2021-08-27) SHIBUTANI, A. B.; SOUZA, M. D.; TREVISOLI, R.; Rodrigo Doria©2021 IEEE.In this article, a current mirror built with junctionless nanowire transistors (JNTs) is investigated for the first time. The study explores the influence of transistors' width on the mirroring precision for input and output devices with different dimensions. The work has been performed through numerical simulations validated with experimental data and showed that the variation of devices' width impacts the output characteristics differently from usually observed in current mirrors formed by inversion mode devices.
- Charge Pumping-Based Method for Traps Density Extraction in Junctionless Transistors(2021) FONTE, E. T.; TREVISOLI, R.; Rodrido Doria© 2021 IEEE.A study of Junctionless Transistors (JNTs) is presented in this work, with emphasis on verifying the extraction of the interface traps density using the charge pumping method. To the best of our knowledge, this is the first work to use this method in JNTs. The method was applied to both simulated and experimental data and has shown satisfactory results.
- Analog operation of junctionless nanowire transistors down to liquid helium temperature(2014-07-09) TREVISOLI, R.; Michelly De Souza; Rodrido Doria; KILCHYTSHA, V.; FLANDRE, D.; Marcelo Antonio PavanelloThe aim of this work is to analyze the analog operation of Junctionless Nanowire Transistors at temperatures down to liquid helium temperature. The analysis is performed in terms of the transconductance, open loop voltage gain and output conductance for experimental long channel devices. It is shown that the temperature reduction can affect significantly the analog performance of the devices. © 2014 IEEE.
- Effect of the temperature on on Junctionless Nanowire Transistors electrical parameters down to 4K(2014-10-29) TREVISOLI, R.; Michelly De Souza; Rodrido Doria; KILCHTYSKA, V.; FLANDRE, D.; Marcelo Antonio PavanelloThe aim of this work is to analyze the operation of Junctionless Nanowire Transistors at liquid helium temperature, focusing the operation at linear regime. The drain current, the transconductance, the low field mobility, subthreshold slope, the interface trap density and the channel resistance are the key parameters under analysis.
- Improved analog operation of junctionless nanowire transistors using back bias(2015-03-18) TREVISOLI, R.; Rodrido Doria; Michelly De Souza; Marcelo Antonio PavanelloThis work reports, for the first time, an analysis of substrate bias on the analog parameters of Junctionless Nanowire Transistors operating as single transistor amplifiers through experimental and simulated data. The study is performed in terms of output conductance, transconductance, open loop voltage gain and transconductance to the drain current ratio. It has been shown that the substrate bias can affect significantly the performance of junctionless devices, such that the positive back bias can reduce the output conductance and improve the voltage gain.
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