Engenharia Elétrica
URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/21
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6 resultados
Resultados da Pesquisa
- The roles of the electric field and the density of carriers in the improved output conductance of junctionless nanowire transistors(2011-01-05) Rodrigo Doria; Marcelo Antonio Pavanello; TREVISOLI, R. D.; Michelly De Souza; LEE, C. W.; FERAIN, I.; DEHDASHTI AKHAVAN, N.; YAN, R.; RAZAVI, P.; YU, R.; KRANTI, A.; COLINGE, J. P.This paper evaluates the roles of the electric field (E) and the density of carries (n) in the drain conductance of Junctionless Nanowire Transistors (JNTs). The behavior of E and n presented by JNTs with the variation of the gate and the drain voltages has been compared to the one presented by Inversion Mode (M) Trigate devices of similar dimensions. It has been shown that the lower drain output conductance exhibited by Junctionless transistors with respect to the IM ones is correlated not only to the differences in the mobility and its degradation but also to the electric field, the density of carries and the first order derivative of these variables with respect the drain voltage. ©The Electrochemical Society.
- Stress relaxation empirical model for biaxially strained triple-gate devices(2011-01-05) TREVISOLI, R. D.; MARTINO, J. A.; SIMOEN, E.; CLAEYS, C.; PAVANELLO, M. A.Multiple gate devices provides short channel effects reduction, been considered promising for sub 20 nm era. Strain engineering has also been considered as an alternative to the miniaturization due to the boost in the carrier mobility. The stress non-uniformity in Multiple gate devices cannot be easily considered in a TCAD device simulation without the coupled process simulation which is a cumbersome task. This work analyses the use of an analytical function to compute accurately the dependence of the strain on the device dimensions. The maximum transconductance gain and the threshold voltage shift are used as key parameters to compare simulated and experimental data. ©The Electrochemical Society.
- Analytical model for the threshold voltage in junctionless nanowire transistors of different geometries(2011-09-02) TREVISOLI, R. D.; Rodrigo Doria; Marcelo Antonio PavanelloJunctionless nanowire transistors (JNTs) are considered promising for the sub-20 nm era. As these devices have a constant doping profile from source to drain, they have a great scalability without the need for rigorously controlled doping and activation techniques. These devices also present a flexible threshold voltage, which strongly depends on the device cross section. This work proposes an analytical model for JNTs. The model is derived from the solution of the Poisson equation with the appropriate boundary conditions. The quantum confinement for devices of reduced dimensions has also been accounted. The threshold voltage in cylindrical and trigate JNTs are analyzed. Tridimensional numerical simulations were performed to validate the model. ©The Electrochemical Society.
- Intrinsic gate capacitances of n-type junctionless nanowire transistors using a three-dimensional device simulation and experimental measurements(2012-09-02) MARINIELLO, G.; Rodrido Doria; TREVISOLI, R. D.; Michelly De Souza; Marcelo Antonio PavanelloJunctionless Nanowire transistors have been recently proposed as an alternative to overcome the short channel effect caused by the reduction of the transistors dimensions. These devices behave like a gated resistor due to the lack of the p-n junctions in the channel/ source and channel/drain regions. The influence of doping concentration, silicon width, silicon height and gate oxide thickness on the intrinsic gate capacitances are presented in this paper by using three-dimensional numerical simulations and experimental results of fabricated devices. Also the influence of the applied drain bias in the components of the intrinsic gate capacitances is addressed. © The Electrochemical Society.
- Application of junctionless nanowire transistor in the self-cascode configuration to improve the analog performance(2012-09-02) Rodrido Doria; TREVISOLI, R. D.; Michelly De Souza; Marcelo Antonio PavanelloThe self-cascode (SC) configuration consists in a series association of two transistors with tied gates usually applied to improve the analog performance of MOS devices. This paper compares the analog parameters of single Junctionless transistors with the ones presented by self-cascode associations composed by two Junctionless devices with identical or different fin widths (symmetric and asymmetric, respectively). The transconductance to the drain current ratio, the Early voltage (VEA) and the intrinsic voltage gain (AV) have been evaluated for both single devices and SC structures. It has been shown that the SC configurations, specially the asymmetric ones, present a strong reduction of the drain conductance (gD) with respect to single devices, resulting in an increase of VEA and AV, which can be higher than 30 dB depending on the bias conditions. © The Electrochemical Society.
- Accounting for short channel effects in the drain current modeling of junctionless nanowire transistors(2012-09-02) TREVISOLI, R. D.; Rodrido Doria; Michelly De Souza; Marcelo Antonio PavanelloJunctionless nanowire transistors have a constant doping profile from source to drain, providing a great scalability without the need of rigorously controlled doping gradients and activation techniques. Therefore, these devices are considered as promising for decananometer era. This work proposes an analytical model for the drain current in junctionless nanowire transistor (JNT) accounting for short channel effects and temperature dependence. Tridimensional numerical simulations of p-type devices have been performed to validate the model. Experimental data of n-type devices have also been used. © The Electrochemical Society.