Engenharia Elétrica
URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/21
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13 resultados
Resultados da Pesquisa
- Electron valence-band tunnelling excess noise in twin-gate silicon-on-insulator MOSFETs(2006-01-05) SIMOEN, E.; CLAEYS. C.; LUKYANCHIKOVA, N.; GARBER, N.; SMOLANKA, A.; DER AGOPIAN, P. G.; MARTINO, J. A.The impact of using a twin-gate (TG) configuration on the Electron Valence-Band (EVB) tunnelling-related floating-body effects has been studied in partially depleted (PD) SOI MOSFETs belonging to a 0.13 μm CMOS technology. In particular, the influence on the so-called linear kink effects (LKEs), including the second peak in the linear transconductance (gm) and the associated Lorentzian noise overshoot was investigated. It is shown that while there is a modest reduction of the second gm peak, the noise overshoot may be reduced by a factor of 2. At the same time, little asymmetry is observed when switching the role of the slave and the master transistor, in contrast to the case of the impact ionization related kink effects. Two-dimensional numerical simulations support the observations and show that both the gm, the second gm peak and the body potential are changed in the TG structure compared with a single transistor. © 2005 Elsevier Ltd. All rights reserved.
- Temperature influence on the gate-induced floating body effect parameters in fully depleted SOI nMOSFETs(2008) AGOPIAN P. G. D.; MARTINO, J, A.; SIMOEN, E.; CLAEYS, C.The temperature influence on the gate-induced floating body effect (GIFBE) in fully depleted (FD) silicon-on-insulator (SOI) nMOSFETs is investigated, based on experimental results and two-dimensional numerical simulations. The GIFBE behavior will be evaluated taking into account the impact of carrier recombination and of the effective electric field mobility degradation on the second peak in the transconductance (gm). This floating body effect is also analyzed as a function of temperature. It is shown that the variation of the studied parameters with temperature results in a "C" shape of the threshold voltage corresponding with the second peak in the gm curve. © 2008 Elsevier Ltd. All rights reserved.
- Threshold voltages of SOI MuGFETs(2008-12-05) de Andrade M.G.C.; Martino J.A.The multiple-gate field-effect transistor (MuGFET) is a device with a gate folded on different sides of the channel region. They are one of the most promising technological solutions to create high-performance ultra-scaled SOI CMOS. In this work, the behavior of the threshold voltage in double-gate, triple-gate and quadruple-gate SOI transistors with different channel doping concentrations is studied through three-dimensional numerical simulation. The results indicated that for double-gate transistors, one or two threshold voltages can be observed, depending on the channel doping concentration. However, in triple-gate and quadruple-gate it is possible to observe up to four threshold voltages due to the corner effect and the different doping concentration between the top and bottom of the Fin. © 2008 Elsevier Ltd. All rights reserved.
- SOI technology characterization using SOI-MOS capacitor(2005) Sonnenberg V.; Martino J.A.In this paper a set of simple methods is presented, to determine the main parameters of the silicon on insulator technology, using a thin film SOI-MOS capacitor. Methods to obtain the effective substrate doping concentration, substrate interface charge density and the buried oxide thickness using the two terminal SOI capacitor are presented. The front gate oxide thickness, the silicon film thickness, the silicon doping concentration and front and back interface charge density are obtained using a three terminal SOI-MOS capacitor. Bidimensional numerical simulations of SOI structure are performed for analyzing the high frequency capacitance vs. voltage curves and to test the proposed methods. These methods were applied experimentally and coherent results were found. © 2004 Elsevier Ltd. All rights reserved.
- A simple current model for edgeless SOI nMOSFET and a 3-D analysis(2005) Giacomini R.; Martino J.A.This work presents a new approach for the current model of thin-film, fully depleted SOI edgeless transistors, based on the asymmetric trapezoidal gate model. The most common current model for an edgeless transistor is obtained by taking the rectangular device drain current expression and substituting the device width by an "equivalent" device width, usually given by the average between source and drain width of the channel. However, this model does not take into account some effects that take place near the corners of the device and that have a significant influence on the current expression. The new model is tested using three-dimensional numerical simulation and experimental data. The proposed model is still simple and both simulation and experimental results show that it presents an improved performance. © 2005 Elsevier Ltd. All rights reserved.
- Analog performance of standard and strained triple-gate silicon-on-insulator nFinFETs(2008) Pavanello M.A.; Martino J.A.; Simoen E.; Rooyackers R.; Collaert N.; Claeys C.This work shows a comparison between the analog performance of standard and strained Si n-type triple-gate FinFETs with high-κ dielectrics and TiN gate material. Different channel lengths and fin widths are studied. It is demonstrated that both standard and strained FinFETs with short channel length and narrow fins have similar analog properties, whereas the increase of the channel length degrades the early voltage of the strained devices, consequently decreasing the device intrinsic voltage gain with respect to standard ones. Narrow strained FinFETs with long channel show a degradation of the Early voltage if compared to standard ones suggesting that strained devices are more subjected to the channel length modulation effect. © 2008 Elsevier Ltd. All rights reserved.
- Advantages of graded-channel SOI nMOSFETs for application as source-follower analog buffer(2008) de Souza M.; Flandre D.; Pavanello M.A.In this work the performance of graded-channel (GC) SOI MOSFETs operating as source-follower buffers is presented. The experimental analysis is performed by comparing the gain and linearity of buffers implemented with GC and standard SOI MOS devices considering the same mask dimensions. It is shown that by using GC devices, buffer gain very close to the theoretical limit can be achieved, with improved linearity, while for standard devices the gain departs from the theoretical value depending on the inversion level imposed by the bias current and input voltage. Two-dimensional numerical simulations were performed in order to confirm some hypotheses proposed to explain the gain behavior observed in the experimental data. By using numerical simulations the channel length has been varied, showing that the gain of buffers implemented with GC devices remains close to the theoretical limit even when short-channel devices are adopted. It has also been shown that the length of a source-follower buffer using GC devices can be reduced by a factor of 5, in comparison with a standard SOI MOSFET, without gain loss or linearity degradation. © 2008 Elsevier Ltd. All rights reserved.
- Evaluation of triple-gate FinFETs with SiO2-HfO2-TiN gate stack under analog operation(2007) Marcelo Antonio Pavanello; MARTINO, J. A.; SIMOEN, E.; ROOYACKERS, R.; COLLAERT, N.; CLAEYS, C.This work presents the analog performance of nMOS triple-gate FinFETs with high-κ dielectrics, TiN gate material and undoped body from DC measurements. Different fin widths and devices with and without halo implantation are explored. No halo FinFETs can achieve extremely large gain and improved unity gain frequency at similar channel length than halo counterparts. The FinFETs with 110 nm long channel achieve an intrinsic gain of 25 dB. Extremely large Early voltages have been measured on long channel nMOS with no halo and relatively wide fins compared to the results usually reported in the literature. The large Early voltage obtained suggests that the devices operate in the onset of volume inversion due to the low doping level of the device body. © 2007 Elsevier Ltd. All rights reserved.
- Analysis of uniaxial and biaxial strain impact on the linearity of fully depleted SOI nMOSFETs(2007) Pavanello M.A.; Martino J.A.; Simoen E.; Claeys C.This work studies the impact of uniaxial, biaxial and combined uniaxial-biaxial strain on the linearity of nMOSFETs from a 65 nm fully depleted (FD) SOI technology. The total harmonic distortion (THD) and third-order harmonic distortion (HD3) will be used as figures of merit. Operation in saturation and triode regimes will be the focus. When biased in the saturation region short-channel devices have been used and biased as single-transistor amplifiers. In this case, at low voltage bias the use of any kind of strain improves the THD in comparison to standard SOI. When operating in linear region as a quasi-linear resistor longer devices were studied. For operation in linear regime the HD3 is nearly the same for all devices and no clear strain influence can be found at similar bias condition. If a target on-resistance is considered, the use of biaxially or combined unxially-biaxially strained films can provide a reduction on the required gate voltage overdrive or a reduction on the device channel width without degrading the HD3. © 2007 Elsevier Ltd. All rights reserved.
- Impact of halo implantation on 0.13 μm floating body partially depleted SOI n-MOSFETs in low temperature operation(2005) Pavanello M.A.; Martino J.A.; Simoen E.; Claeys C.This work studies the effect of halo implantation on the electrical characteristics of deep-submicrometer partially depleted SOI nMOSFETs during low temperature and floating body operation. Parameters such as the drain induced barrier lowering (DIBL) and the device thermal resistance have been investigated. It is shown that the combination of floating body operation with halo implantation degrades the DIBL in the temperature range studied (90 K-300 K) in comparison to devices that did not received this implantation. The halo region causes a more pronounced negative output conductance than for the transistors without a halo implantation. An estimation of the temperature rise for a given dissipated power in both types of devices is made, based on the thermal resistance, which is derived from the output characteristics in function of the temperature. © 2005 Elsevier Ltd. All rights reserved.