Engenharia Elétrica
URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/21
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36 resultados
Resultados da Pesquisa
- Electron valence-band tunnelling excess noise in twin-gate silicon-on-insulator MOSFETs(2006-01-05) SIMOEN, E.; CLAEYS. C.; LUKYANCHIKOVA, N.; GARBER, N.; SMOLANKA, A.; DER AGOPIAN, P. G.; MARTINO, J. A.The impact of using a twin-gate (TG) configuration on the Electron Valence-Band (EVB) tunnelling-related floating-body effects has been studied in partially depleted (PD) SOI MOSFETs belonging to a 0.13 μm CMOS technology. In particular, the influence on the so-called linear kink effects (LKEs), including the second peak in the linear transconductance (gm) and the associated Lorentzian noise overshoot was investigated. It is shown that while there is a modest reduction of the second gm peak, the noise overshoot may be reduced by a factor of 2. At the same time, little asymmetry is observed when switching the role of the slave and the master transistor, in contrast to the case of the impact ionization related kink effects. Two-dimensional numerical simulations support the observations and show that both the gm, the second gm peak and the body potential are changed in the TG structure compared with a single transistor. © 2005 Elsevier Ltd. All rights reserved.
- Temperature influence on the gate-induced floating body effect parameters in fully depleted SOI nMOSFETs(2008) AGOPIAN P. G. D.; MARTINO, J, A.; SIMOEN, E.; CLAEYS, C.The temperature influence on the gate-induced floating body effect (GIFBE) in fully depleted (FD) silicon-on-insulator (SOI) nMOSFETs is investigated, based on experimental results and two-dimensional numerical simulations. The GIFBE behavior will be evaluated taking into account the impact of carrier recombination and of the effective electric field mobility degradation on the second peak in the transconductance (gm). This floating body effect is also analyzed as a function of temperature. It is shown that the variation of the studied parameters with temperature results in a "C" shape of the threshold voltage corresponding with the second peak in the gm curve. © 2008 Elsevier Ltd. All rights reserved.
- Threshold voltages of SOI MuGFETs(2008-12-05) de Andrade M.G.C.; Martino J.A.The multiple-gate field-effect transistor (MuGFET) is a device with a gate folded on different sides of the channel region. They are one of the most promising technological solutions to create high-performance ultra-scaled SOI CMOS. In this work, the behavior of the threshold voltage in double-gate, triple-gate and quadruple-gate SOI transistors with different channel doping concentrations is studied through three-dimensional numerical simulation. The results indicated that for double-gate transistors, one or two threshold voltages can be observed, depending on the channel doping concentration. However, in triple-gate and quadruple-gate it is possible to observe up to four threshold voltages due to the corner effect and the different doping concentration between the top and bottom of the Fin. © 2008 Elsevier Ltd. All rights reserved.
- Impact of SEG on uniaxially strained MuGFET performance(2011-05-05) Paula Agopian; PACHECO, V. H.; MARTINO J. A.; SIMOEN, E.; CLAEYS, C.This work focuses on the impact of the source and drain Selective Epitaxial Growth (SEG) on the performance of uniaxially strained MuGFETs. With the channel length reduction, the normalized transconductance (gm.L/W) of unstressed MuGFETs decreases due to the series resistance and short channel effects (SCE), while the presence of uniaxial strain improves the gm. The competition between the series resistance (Rs) and the uniaxial strain results in a normalized gm maximum point for a specific channel length. Since the SEG structure influences both Rs and the strain in the channel, this work studies from room down to low temperature how these effects influence the performance of the triple-gate FETs. For lower temperatures, the strain-induced mobility enhancement increases and leads to a shift in the maximum point towards shorter channel lengths for devices without SEG. This shift is not observed for devices with SEG where the strain level is much lower. At 150 K the gm behavior of short channel strained devices with SEG is similar to the non SEG ones due to the better gm temperature enhancement for devices without SEG caused by the strain. For lower temperatures SEG structure is not useful anymore. © 2011 Elsevier Ltd. All rights reserved.
- Stress engineering and proton radiation influence on off-state leakage current in triple-gate SOI devices(2013-01-05) AGOPIAN, P. G. D.; BORDALLO, C. C. M.; SIMOEN, E.; CLAEYS, C.; MARTINO, J. A.In this work the influence of different stress techniques and proton irradiation on the off-state leakage current is investigated for p- and n-channel Multiple Gate MOSFETs (MuGFETs). Four different splits are evaluated: unstrained, uniaxially stressed, biaxially stressed and the combination of both types of stress. For nMuGFETs, the higher the stress effectiveness the higher is the GIDL due to band gap narrowing. However for p-channel devices, the gate leakage current is higher than band-to-band tunneling and it dominates the drain current in the off-state region. After proton irradiation all the n-channel devices present a worse behavior. Off-state leakage current for nMuGFETs was degraded by radiation due to the increase of the back gate leakage current generated by the increase of the interface charge density at the back interface. For p-channel devices, the radiation did not show any influence in off-state leakage current, since the gate oxide thickness is very thin and therefore the radiation has no influence on the gate current, which is the dominant effect in the pMuGFETs off-state region. © 2013 Elsevier Ltd. All rights reserved.
- SOI technology characterization using SOI-MOS capacitor(2005) Sonnenberg V.; Martino J.A.In this paper a set of simple methods is presented, to determine the main parameters of the silicon on insulator technology, using a thin film SOI-MOS capacitor. Methods to obtain the effective substrate doping concentration, substrate interface charge density and the buried oxide thickness using the two terminal SOI capacitor are presented. The front gate oxide thickness, the silicon film thickness, the silicon doping concentration and front and back interface charge density are obtained using a three terminal SOI-MOS capacitor. Bidimensional numerical simulations of SOI structure are performed for analyzing the high frequency capacitance vs. voltage curves and to test the proposed methods. These methods were applied experimentally and coherent results were found. © 2004 Elsevier Ltd. All rights reserved.
- Diamond MOSFET: An innovative layout to improve performance of ICs(2010) Gimenez S.P.A new planar MOSFET structure is proposed through a simple layout change, which modifies the gate geometric shape from rectangular to hexagonal in order to use the "corner effect concept" to enhance the resultant longitudinal (parallel) electric field, drift velocity of mobile carriers in the channel, drain current, transconductance, Early voltage and on-resistance in comparison to the equivalent conventional parameters. This paper is conceptual and performs a comparative analyzes between conventional and Diamond Partially-Depleted SOI nMOSFETs by 3D numerical simulations to understand the advantages and disadvantages of this innovative device compared to the conventional counterpart, keeping the same gate area, geometric factor and bias conditions. A simple analytical model for the drain current was proposed and tested for the Diamond transistor. Since we found better results of the Diamond SOI nMOSFETs we believe that, this innovative layout can be a new alternative for analog and digital integrated circuit applications for whatever area it may be needed, without any extra burden to the current technology. This layout approach can also be applied for any planar or 3D transistors technologies. © 2010 Elsevier Ltd. All rights reserved.
- Different stress techniques and their efficiency on triple-gate SOI n-MOSFETs(2015) Buhler R.T.; Agopian P.G.D.; Collaert N.; Simoen E.; Claeys C.; Martino J.A.© 2014 Elsevier Ltd. All rights reserved.Three techniques to implement mechanical stress in n-channel Multiple Gate MOSFETs (MuGFETs) are investigated through 3D simulations and transconductance measurements. They are: uniaxial stress, biaxial stress and biaxial + uniaxial stress. Four different fin dimensions are evaluated: a narrow and a wide transistor, combined with a short or a long device. It is shown that the stress distribution and the device performance exhibit a dependence on the fin dimensions. For uniaxially strained devices, the dimensions are important as the bending of the silicon required to induce stress in the channel depends on its size. However, for biaxially strained devices the plane of etching in the silicon fin is important, determining the degradation of the stress components. The combination of the two types of stress results in an improvement of some stress components and an overall improvement in the maximum transconductance.
- A simple current model for edgeless SOI nMOSFET and a 3-D analysis(2005) Giacomini R.; Martino J.A.This work presents a new approach for the current model of thin-film, fully depleted SOI edgeless transistors, based on the asymmetric trapezoidal gate model. The most common current model for an edgeless transistor is obtained by taking the rectangular device drain current expression and substituting the device width by an "equivalent" device width, usually given by the average between source and drain width of the channel. However, this model does not take into account some effects that take place near the corners of the device and that have a significant influence on the current expression. The new model is tested using three-dimensional numerical simulation and experimental data. The proposed model is still simple and both simulation and experimental results show that it presents an improved performance. © 2005 Elsevier Ltd. All rights reserved.
- An in-depth analysis of temperature effect on DIBL in UTBB FD SOI MOSFETs based on experimental data, numerical simulations and analytical models(2017) Pereira A.S.N.; de Streel G.; Planes N.; Haond M.; Giacomini R.; Flandre D.; Kilchytska V.© 2016 Elsevier LtdThe Drain Induced Barrier Lowering (DIBL) behavior in Ultra-Thin Body and Buried oxide (UTBB) transistors is investigated in details in the temperature range up to 150 °C, for the first time to the best of our knowledge. The analysis is based on experimental data, physical device simulation, compact model (SPICE) simulation and previously published models. Contrary to MASTAR prediction, experiments reveal DIBL increase with temperature. Physical device simulations of different thin-film fully-depleted (FD) devices outline the generality of such behavior. SPICE simulations, with UTSOI DK2.4 model, only partially adhere to experimental trends. Several analytic models available in the literature are assessed for DIBL vs. temperature prediction. Although being the closest to experiments, Fasarakis’ model overestimates DIBL(T) dependence for shortest devices and underestimates it for upsized gate lengths frequently used in ultra-low-voltage (ULV) applications. This model is improved in our work, by introducing a temperature-dependent inversion charge at threshold. The improved model shows very good agreement with experimental data, with high gain in precision for the gate lengths under test.