Engenharia Elétrica
URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/21
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7 resultados
Resultados da Pesquisa
- Modeling Quantum Confinement in Multi-Gate Transistors with Effective Potential(2022) SOARES, C. S.; BAIKADI, P. K. R.; ROSSETO, A. C. J.; Marcelo Antonio Pavanello; VASILESKA, D.; WIRTH, G. I.© 2022 IEEE.Particle-based Monte Carlo device simulators are an efficient tool to investigate the performance and reliability of transistors. The semiclassical theoretical model employed in the Monte Carlo device simulator is unsuccessful to describe some aspects of the multi-gate transistors that come from the quantum behavior of charge carriers. To take into consideration the space-quantization effects in these simulators, a quantum correction is necessary. We propose to include an effective potential in the Monte Carlo device simulator to address the wave-like behavior of electrons in n-type silicon FinFET and n-type silicon nanowire transistors. The effective potential has a unique parameter, which can be adjusted to find a line density using an Effective Potential-Poisson solver that matches with the line density calculated using a Schrodinger-Poisson solver. We demonstrated that using the effective potential model, the effect of the electron confinement is well described.
- Junctionless Nanowire Transistor for Analog Applications: Cascode Current Mirror Configuration(2022-08-05) SHIBUTANI, A. B.; TREVISOLI, R.; Rodrigo Doria© 2022 IEEE.In this paper, a cascode current mirror compounded by junctionless nanowire transistors is analyzed for the first time. Thus, the performance and the mirroring precision of the configuration were investigated considering the internal circuit feedback and the high output resistance. On this basis, symmetrical and asymmetrical configurations were examined to comprehend the junctionless nanowire transistor behavior as a current source.
- Analysis of Variability in Transconductance and Mobility of Nanowire Transistors(2022-08-22) SILVA, L. M. B. DA; Marcelo Antonio Pavanello; CASSE, M.; BARRAUD, S.; VINET, M.; FAYNOT, O.; Michelly De Souza© 2022 IEEE.This work presents a comparison between the variability in junctionless nanowire transistors and inversion-mode nanowire transistors, looking at the transconductance, low-field mobility, linear and quadratic mobility degradation coefficients. To extract these parameters, the Y-Function method has been used. The obtained results shows differences in mobility and transconductance matching coefficients, indicating that mobility influence is not the only source of transconductance variation.
- Impact of Temperature Effects in the Zero Temperature Coefficient of the Ellipsoidal MOSFET(2022-08-22) DE LIMA, M. P. B.; PEIXOTO, M. A. P.; CORREIA, M. M.; GALEMBECK, E. H. S.; Salvador Gimenez; CAMILO, L. M.© 2022 IEEE.The zero temperature coefficient (ZTC) is investigated by the simple model and three-dimensional numerical simulations in the Metal-Oxide-Semiconductor (MOS) Field Effect Transistor (MOSFET) with the ellipsoidal (EM) and conventional rectangular gate geometries (CM), considering the same channel widths (W), gate areas (AG) and bias condition (BC) technology. A simple model is used to study the behavior of the gate voltage at ZTC (VZTC) in the linear and the saturation region. The influence of the temperature mobility degradation on VZTC is analyzed for EM and CM devices. The VZTC changes in the temperature range investigated showed a temperature mobility degradation dependence and the both devices showed the same behavior. The analysis takes into account temperature dependence model parameters such as threshold voltage and mobility. The analytical predictions are in very close agreement with 3D simulations results in spite of the simplification used for the VZTC model as a function of temperature in the linear and the saturation region.
- Impact of using Octogonal Layout Style in Planar Power MOSFETs(2022-08-22) DA SILVA, G. A.; Salvador Gimenez© 2022 IEEE.Previous studies have already shown that the use of alternative gate shapes for planar and tridimensional MOSFETs are capable of boosting their analog and digital electrical performances and their ionizing radiations robustness. In this scenario, this work has the objective to study the impact of the use of octagonal layout style (OCTO), as the basic cell, to the implementing of the Planar Power MOSFET (PPM). The main results of this paper show that the PPM layouted with OCTO layout styles, as the basic cells, are able to improve the drain saturation current (IDS-sat) about 668%%, in relation to that implemented with conventional rectangular layout style, considering that they present the same gate area and bias conditions. Therefore, this type of layout approach can be considered an alternative layout to improve the electrical performance of PPMs.
- Experimental Comparison of Junctionless and Inversion-Mode Nanowire MOSFETs Electrical Properties at High Temperatures(2022-08-22) PRATES, R. R.; BARRAUD, S.; CASSE, M.; VINET, M.; FAYNOT, O.; Marcelo Antonio Pavanello© 2022 IEEE.This work aims to present the electrical properties of junctionless and inversion-mode nanowires MOSFETs in the temperature range from 300 K to 580 K. Devices with different fin widths are compared. The comparison is performed using experimental data looking for some of the fundamental electrical parameters of these transistors such as threshold voltage, inverse subthreshold slope, current, and carrier mobility over the temperature.
- Standard MOS Diodes Composed by SOI UTBB Transistors(2022-08-05) COSTA, F. J.; TREVISOLI, R.; CAPOVILLA, C. E.; Rodrigo Doria© 2022 IEEE.The main objective of this work is to present an analysis of the performance of UTBB SOI transistors working as standard diodes, where the implementation of ground planes and substrate bias are analyzed. It is shown a reduced leakage current and increased ratio between the on and off-state currents with the substrate bias at -2 V and with a P-type GP implemented. However, both conditions result in increased threshold voltage.