Engenharia Elétrica
URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/21
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8 resultados
Resultados da Pesquisa
- Impact in the Parallel Processing of IHM-Plasma Using the Earliest-Deadline-First Algorithm for the Task-Scheduler Realized by Hardware(2023-05-05) KRAUSE, I.; DANTA, L. P.; Salvador Gimenez© 2023, Brazilian Microelectronics Society. All rights reserved.This work studies the impact in the parallel processing of the Interlocked-Hardware-Microkernel (IHM) Plasma microprocessor (IHM-Plasma) by implementing the Earliest-Deadline-First (EDF) algorithm by hardware in the task-scheduler block that belongs to those task-based operational systems, such as that related to the real-time operational systems (RTOS). IHM-Plasma presents Reduced Instruction Set Computer (RISC) architecture. Results show that the EDF algorithm running in IHM-Plasma's hardware has increased the number of tasks executed per second by up to 174% compared to the same algorithm running in software. The developed work has great potential use in Hard Real-Time Systems and others where a rigid control of deadlines is essential and hold many tasks.
- Performance of SOI Ω-Gate Nanowires from Cryogenic to High Temperatures(2022-09-17) Marcelo Antonio Pavanello; Michelly De Souza© 2022, Brazilian Microelectronics Society. All rights reserved.—This review paper presents the electrical characteristics of Silicon-On-Insulator Ω-Gate nanowires in a wide range of temperatures. The operation in cryogenic and high-temperature environments will be experimentally explored. The influence of nanowire width and channel length will be dis-cussed. Nanowires with and without strain will be investigated from room temperature down to cryogenic ones, showing that strained nanowires improve carrier mobility in the whole temperature range. At high temperatures, it is demonstrated that nanowires can operate successfully up to 580 K, maintaining the ideal body factor. The effect of high temperatures on Gate-In-duced Drain Leakage will also be studied. The experimental re-sults in the whole temperature range confirm that SOI nan-owires are an excellent alternative for FinFET replacement in future technological nodes.
- The Second Generation of Layout Styles to Further Boost the Electrical Performance of Analog MOSFETs(2022-09-17) SILVA, G. A. DA; Salvador Gimenez© 2022, Brazilian Microelectronics Society. All rights reserved.Previous studies have shown that the first generation of layout styles composed by the Diamond (hexagonal), Octo (octagonal), and Ellipsoidal gate shapes for the imple-menting of the planar and three-dimensional Metal-Oxide-Semiconductor (MOS) Field Effect Transistors (MOSFETs) are capable of boosting their analog and digital electrical per-formances, ionizing radiation tolerances, and reducing the die areas used in comparison to those transistors designed with conventional rectangular layout styles. In order to further boost these features obtained by the use of the first generation of layout styles, one of elements of the second generation of layout styles for MOSFETs, entitled Half-Diamond, is being intro-duced. This new proposal is an evolution of the Diamond layout style, which is able to preserve the Longitudinal Corner Effect (LCE), the Parallel Connection of MOSFETs with Different Channel Lengths Effect (PAMDLE), and the Deactivation of Parasitic MOSFETs in Bird’s Beaks Regions (DEMPAMBBRE) effects promoted by the first generation. This layout style can also reduce the effective channel lengths of MOSFETs in comparison to those reached by the Diamond layout style. In this context, this work performs an experimental comparative study between the electric performances of MOSFETs implemented with the Half-Diamond, Diamond, and Conventional layout styles, considering they present the same gate areas, bias conditions, and the 180 nm Bulk CMOS ICs technology node. The experimental results show that the satu-ration drain current normalized by the aspect ratio and low-frequency open-loop voltage gain, in dB, of MOSFET implemented with the Half-Diamond layout style (HDM) are 17% and 3.5% higher, respectively, than those found in MOSFETs counterparts, designed with the conventional rectangular gate shape (CMs).
- Reliability analysis of gamma-and X-ray TID effects, on a commercial AlGaN/GaN based FET(2021-01-05) BÔAS, A. C. V.; ALBERTON, S. G.; MEDINA, N. H.; AGUIAR, V. A. P.; MELO, M. A. A.; Roberto Santos; Renato Giacomini; CAVALCANTE, T. C.; VAZ, R. G.; JUNIOR E, C. F. P.; SEIXAS, L. E.; FINCO, S.; Marcilei Aparecida Guazzelli© 2021, Brazilian Microelectronics Society. All rights reserved.—In this work, measurements were taken to investigate the robustness of a GaN HEMT to Total Ionizing Dose (TID) by a60gmmax values are dependable of the dose rate.DVTH values due to the TID, in this device are independent of the dose rate and the radiation source. However, the DCo Source. These results will be compared with a previous X-ray based work. Therefore, we will be, primarily, comparing both radiation sources. The robustness was investigated through IDxV curves and characteristic parameters of the irradiated device. The analysis included data acquired both from on-and off-state modes. The work concludes that the device is robust to TID, as it quickly recovered important parameters. Manly, the on-state mode, which presented a better performance compared to the off-mode. An analogous behavior was seen for X-ray. Finally, the.
- Using the hexagonal layout style for mosfets to boost the device matching in ionizing radiation environments(2020-01-05) PERUZZI, V. V.; CRUZ, W. S.; SILVA, G. A.; SIMOEN, E.; CLAEYS, C.; Salvador Gimenez© 2020, Brazilian Microelectronics Society. All rights reserved.This paper describes an experimental comparative study of the mismatching between the Diamond (hexagonal gate geometry) and Conventional (rectangular gate shape) n-chan-nel Metal-Oxide-Semiconductor (MOS) Field Effect Transistors (MOSFETs), which were manufactured in an 130 nm Sili-con-Germanium Bulk Complementary MOS (CMOS) technology and exposed to different X-rays Total Ionizing Doses (TIDs). The results indicate that the Diamond layout style with an alpha (α) angle equal to 90˚ for MOSFETs is capable of re-ducing the device mismatching by at least 17% regarding the electrical parameters studied as compared to the Conventional MOSFET (CnM) counterparts. Therefore, the Diamond layout style can be considered an alternative hardness-by-design (HBD) layout strategy to boost the electrical performance and TID tolerance of MOSFETs.
- Zero temperature coefficient behavior for ellipsoidal mosfet(2020-01-05) BRAGA DE LIMA, M. P.; CAMILO, L. M.; PEIXOTO, M. A. P.; CORREIA, M. M.; Salvador Gimenez© 2020, Brazilian Microelectronics Society. All rights reserved.The zero temperature coefficient (ZTC) is investi-gated by three-dimensional numerical simulations in the Metal-Oxide-Semiconductor (MOS) Field Effect Transistor (MOSFET) with the ellipsoidal (EM) and conventional rectan-gular gate geometries (CM), considering the same channel widths (W), gate areas (AG) and bias condition (BC). In this work an improved simple model which predicts the ZTC point taking into account only the mobility degradation factor (c) and threshold voltage (Vth) parameters as function of temperature is proposed in the linear and saturation operation regions. The analysis takes into account the temperature variations of the threshold voltage and the mobility degradation factor. Alt-hough simple, the model predictions present a good agreement with the numerical simulations results.
- Analysis of the correlation between NBTI effect and the surface potential in junctionless nanowire transistors(2020-01-05) GRAZIANO JUNIOR, N.; TREVISOLI, R.; Rodrido Doria© 2020, Brazilian Microelectronics Society. All rights reserved.— This paper discusses the nature of degradation by NBTI effect in pMOS junctionless nanowire transistors when varying the density of interface traps. The data obtained in simulations are analyzed through the extracted hole density to-gether with the surface potential and it is demonstrated how the quality of gate oxide affects the performance of such transistors, when the density of traps, the channel width, the doping con-centration and the gate bias are varied.
- Effect of substrate bias and temperature variation in the capacitive coupling of soi utbb mosfets(2021-08-23) DA SILVA, E. M.; TREVISOLI, R.; Rodrido Doria© 2021, Brazilian Microelectronics Society. All rights reserved.In this work, the electrical features related to the capacitive coupling and temperature influence of the Ultra-Thin Body and Buried Oxide SOI MOSFET (UTBB) transistors are explored through numerical simulations calibrated to experimental data. The impact of the substrate bias is observed for a set of values ranging from-3 V to 2 V for a temperature range between 100 K and 400 K. Also, structures with n-and ptype ground planes (GP-P and GP-N) and without GP have been evaluated. This approach analyzes the capacitive coupling through the body factor and shows that the negative biasing for all GP types significantly improves the structure coupling and that the device with P-type ground plane has the lowest value of body factor for all the evaluated conditions. The dependence of the body factor on the temperature has shown to be negligible for longer devices. However, for devices shorter than 50 nm, the position of the maximum electrons concentration inside the silicon layer may affect the capacitive coupling.