Engenharia Elétrica
URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/21
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3 resultados
Resultados da Pesquisa
- Asymmetric self-cascode configuration to improve the analog performance of SOI nMOS transistors(2011-10-11) Michelly De Souza; FLANDRE, D.; Marcelo Antonio PavanelloIn this work an asymmetric self-cascode (SC) structure implemented in a 150nm technology have been studied as a function of the threshold voltage and length of both transistors in the structure, aiming to improve the analog characteristics of FD SOI transistors. Experimal results indicate that this structure provided improvement in comparison to single and symmetric (SC) transistors, and that it depends on the saturation voltage of both transistors. The effect of threshold voltage and length variation of both transistors have been analyzed through 2D numerical simulations. The obtained results showed that the analog characteristics of the A-SC is improved both by reducing V T,2 and increasing L 1 and/or L 2, although there would be a maximum M 2 length in which no significant g D reduction is observed. By properly choosing these parameters, a g D reduction of more than one order of magnitude can be achieved. The A-SC has shown to provide an intrinsic voltage gain improvement of more than 20dB in comparison to single devices with similar effective channel length. © 2011 IEEE.
- Uniaxial stress efficiency for different fin dimensions of triple-gate SOI nMOSFETs(2011-10-06) BÜHLER, Rudolf Theoderich; AGOPIAN, P. G. D.; Renato Giacomini; SIMOEN, E.; CLAEYS, C.; MARTINO, J. A.The stress profiles extracted showed that the variation in the silicon fin dimensions influence the stress levels and distributions along the silicon fin. From the analog performance view, these variations in the stress have influence on some electric parameters. The reduction of the total fin length showed no significant change in the parameters, although a reduction in the stress level was noticed, leading to the conclusion that the shift in the stress level is too small to cause a pronounced impact on the parameters. On the other hand, the reduction of the silicon fin height showed more interesting results. Despite that the standard device with smaller fin height presented a lower intrinsic voltage gain performance when compared to the reference device, when implementing strain it supersedes the reference device and presented an enhancement in the intrinsic voltage gain over the standard one up to 8 %, larger than the 5.1 % obtained for the reference device. © 2011 IEEE.
- Liquid helium temperature analog operation of asymmetric self-cascode FD SOI MOSFETs(2012-10-04) Michelly De Souza; KILCHTYSKA, V.; FLANDRE, D.; Marcelo Antonio PavanelloFully Depleted (FD) SOI technology is well known to provide improved analog performance of CMOS transistors [1, 2]. However, FD SOI transistors may suffer from parasitic bipolar effects (PBE) that cause the degradation of the output conductance [3]. The use of cascode transistors with common gate (making a self-cascode-SC topology) has been shown to reduce the output conductance of MOSFETs, while keeping some advantages of long-channel transistors [4]. Fig. 1 represents the self-cascode transistor, composed by transistors MS and MD, with channel lengths LS and LD, and threshold voltages VT, S and VT, D, respectively (with VT, S = VT, D in the symmetric SC-S-SC). Recent works [5, 6] showed that the use of different threshold voltages (VT) for MS and MD (so-called asymmetric self-cascode-A-SC) is able to further enhance the analog properties of SC n-and pMOS transistors, in comparison to the S-SC, at room temperature (RT). In this paper the enhanced analog performance of asymmetric SC structure is experimentally demonstrated at deep cryogenic environments emphasizing its capability to minimize (or even suppress) PBE in FD SOI n-and p-type MOSFETs at liquid helium temperature (LHT), where this effect is more pronounced [7]. © 2012 IEEE.