Engenharia Elétrica
URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/21
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9 resultados
Resultados da Pesquisa
- Junctionless nanowire transistors effective channel length extraction through capacitance characteristics(2023-10-05) SILVA, E. M.; TREVISOLI, R.; Rodrigo Doria© 2023 Elsevier LtdThis work aims to extract the effective channel length (LEFF) of Junctionless Nanowire Transistors (JNT) through the maximum gate capacitance of the devices. The LEFF extraction has been done by extrapolating the maximum gate capacitance as a function of the devices’ channel length (LMASK) and has shown that LEFF is around 10–15 nm longer than LMASK for devices of different channel doping concentrations.
- Impact of series resistance on the drain current variability in inversion mode and junctionless nanowire transistors(2023-10-05) SILVA, L. M. B. DA; Marcelo Antonio Pavanello; CASSÉ, M.; BARRAUD, S.; VINET, M.; FAYNOT, O.; Michelly De Souza© 2023 Elsevier LtdThis work analyzes the influence of source-drain series resistance variability over the drain current in junctionless and inversion mode nanowire transistors. A comparison between drain current and Y-function variability is presented using experimental data of nanowires with different widths and channel lengths. The source-drain series resistance variability is also presented. The results indicates that source-drain series resistance influence is higher on drain current variability for junctionless than inversion mode nanowire transistors.
- Interface traps density extraction through transient measurements in junctionless transistors(2022-08-05) TEICEIRA DA FONTE, E.; TREVISOLI, R.; BARRAUD S.; Rodrigo Doria© 2022 Elsevier LtdThis paper presents an extraction method for the interface traps density on Junctionless Transistors (JNTs) using an adapted charge pumping technique. To the best of our knowledge, this is the first work to apply this method in JNTs. Initially, it was stated through numerical simulations that a transient current, which increases with the trap density, is observed in the devices when the charge pumping method is applied. Then, a measurement setup was proposed to extract the pumping current resultant from a gate pulse and a mathematical expression was proposed to extract the density of trapped charges in the Oxide/Silicon interface (Nit). Aiming to demonstrate the method applicability for determining the JNTs interface quality, it was applied to simulations considering different trap densities as well as to experimental data of Junctionless Nanowire Transistors. It was observed that the method accuracy increases for larger trap densities and presents agreement to theoretical data for Nit > 1 × 1011 cm−2.
- Influence of fin width variation on the electrical characteristics of n-type junctionless nanowire transistors at high temperatures(2021-11-21) RIBEIRO, T. A.; BERGAMASCHI, F.E.; BARRAUD, S.; Marcelo Antonio PavanelloThis work studied the effects of the fin width variation on Silicon-on-Insulator Junctionless Nanowire Transistors (JNTs) working in the temperature range of 300 K to 500 K. The effects of the temperature on the measured drain current and gate capacitance, and on the extracted electrical parameters such as the threshold voltage, the subthreshold slope, and the electron mobility were analyzed. Results show that JNTs with larger fin width may present better carrier mobility at a higher temperature than narrow ones as the degradation due to phonon scattering is decreased and the impurity scattering becomes more relevant. It is demonstrated that JNTs with narrow fin width show higher phonon scattering and higher mobility variation with the temperature than wider ones.
- Influence of interface traps density and temperature variation on the NBTI effect in p-Type junctionless nanowire transistors(2021-12-05) GRAZIANO, N.; COSTA, F. J.; TREVISOLI, R.; BARRAUD, S.; Rodrigo Doria© 2021 Elsevier LtdThis paper deals with the behavior of degradation by NBTI effect in pMOS junctionless nanowire transistors (JNTs). The analysis has been performed through measurements followed by 3D numerical simulations and has shown that the increase in the oxygen precursors density close to the interface leads to the reduction of the saturation in the NBTI effect when the devices operate in partial depletion regime. Such effect can be associated to the change in the flatband voltage to more negative values as well as the threshold voltage with the increase in the precursor density. In the sequence of the work, it was shown that, as the operation temperature rises, there is an increase in the degradation of the threshold voltage due to NBTI, which is more pronounced for larger gate voltages. It was concluded that this effect could be associated to the increase in the recombination rate with the temperature, which enables the occupation of a larger amount of traps.
- Junctionless nanowire transistors parameters extraction based on drain current measurements(2019) Trevisoli R.; Doria R.T.; de Souza M.; Barraud S.; Pavanello M.A.© 2019 Elsevier LtdThe aim of this work is to propose and qualify a systematic method for parameters extraction of Junctionless Nanowire Transistors (JNTs) based on drain current measurements and compact modeling. As junctionless devices present a different conduction mechanism than inversion-mode transistors, the methods developed for the latter devices either are not compatible or cannot be directly applied to JNTs before a deep analysis on their applicability. The current work analyzes the extraction of the series resistance, including a discussion about the influence of the first and second order mobility degradation factors, flatband voltage and low field mobility in junctionless transistors based only on static drain current curves. An analysis of the method accuracy considering the influence of the channel length, nanowire width and height, gate oxide thickness and doping concentration is also presented for devices with different characteristics through three-dimensional numerical simulations. The inclusion of the second order effects in a drain current model is also shown, considering the extracted values. The method applicability is also successfully demonstrated in experimental devices.
- Compact modeling of triple gate junctionless MOSFETs for accurate circuit design in a wide temperature range(2019) Pavanello M.A.; Cerdeira A.; Doria R.T.; Ribeiro T.A.; Avila-Herrera F.; Estrada M.© 2019 Elsevier LtdThis paper presents the extension of proposed physically-based continuous compact analytical model of triple gate junctionless nanowire transistors for accurate description of device electrical characteristics in a wide temperature range from room temperature up to 500 K. The model validation is performed by comparison against tridimensional numerical simulation and experimental data showing very good agreement, with continuous description of drain current and its derivatives in all regions of operation and temperatures.
- Low-frequency noise and effective trap density of short channel p- and n-types junctionless nanowire transistors(2014) Doria R.T.; Trevisoli R.; De Souza M.; Pavanello M.A.This work presents an evaluation of the Low-Frequency Noise (LFN) exhibited by short-channel Junctionless Nanowire Transistors (JNTs). Unlike in previous works in which only the noise of n-type transistors was evaluated, this paper exhibits an analysis of both the LFN and the effective trap density of n- and p-type JNTs. The low-frequency noise is analyzed in terms of the channel length as well as doping concentration and has shown to be nearly independent on the former parameter when the device is biased above threshold and to decrease with the raise of the latter. Also, carrier number fluctuations dominate the LFN in nMOS JNTs whereas an important mobility fluctuation component is present in the pMOS ones. The effective trap density of JNTs has shown to be in the order of 1019 cm-3 eV-1, presenting its maximum around 1.4 nm away from the silicon/gate dielectric interface independently on the device type or doping concentration. © 2014 Elsevier Ltd. All rights reserved.
- A physically-based threshold voltage definition, extraction and analytical model for junctionless nanowire transistors(2013) Trevisoli R.D.; Doria R.T.; De Souza M.; Pavanello M.A.This work proposes a physically-based definition for the threshold voltage, VTH, of junctionless nanowire transistors and a methodology to extract it. The VTH is defined as the point of equal magnitude for the drift and diffusion components of the drain current. The methodology for VTH extraction uses the device transconductance over drain current ratio characteristics. An analytical model for the threshold voltage based on the same definition has also been developed. Both VTH extraction method and model have been validated through 3D simulations and have been applied to experimental devices. The proposed method has shown to provide a correct dependence on the temperature, while the double derivative of the drain current method overestimates this variation. © 2013 Elsevier Ltd. All rights reserved.