Engenharia Elétrica
URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/21
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4 resultados
Resultados da Pesquisa
Artigo de evento 1 Citação(ões) na Scopus Behavior of Graded Channel SOI Gate-All-Around nMOSFET devices at high temperatures(2004-09-11) SANTOS, C. D. G. DOS; Marcelo Antonio Pavanello; MARTINO, J. A.; FLANDRE, D.; RASKIN, J.-P.This paper presents the behavior of Graded Channel SOI Gate-All-Around (GAA) nMOSFET at high temperatures in the range of 27°C to 300°C. Threshold voltage, subthreshold slope, maximum transconductance, zero temperature coefficient and Early voltage were investigated through three-dimensional simulations and electrical characterization. It was verified that when temperature increases, threshold voltage decreases, subthreshold slope increases and did not suffer any degradation with the LLD/L ratio increase. The maximum transconductance decreases when temperature increases, and increases for larger LLD/L ratios, and Early voltage decreases almost linearly with temperature increase. The results show the excellent behavior of GC SOI GAA nMOSFET at high temperatures compared to conventional SOI GAA devices.Artigo de evento 0 Citação(ões) na Scopus Implementation of tunable resistors using graded-channel SOI MOSFETs operating in cryogenic environments(2005-09-07) Marcelo Antonio Pavanello; CERDEIRA, A.; MARTINO, J. A.; ALEMAN, M. A.; FLANDRE, D.The performance evaluation of conventional and graded-channel SOI MOSFETs operating as tunable resistors is performed from room temperature down to 90 K. The on-resistance, total harmonic distortion and third order harmonic distortion have been adopted as figures of merit. It is shown that the on-resistance reduces with the temperature lowering and is smaller in any GC SOI than in conventional SOI due to the effective channel length reduction. The total harmonic distortion is weakly temperature dependent and decreases in GC transistors, due to reduction of the effective voltage amplitude that is applied on the conventionally doped part of the channel. On the other hand, the third order harmonic distortion is strongly temperature influenced, increasing 15 dB at 90 K with respect to room temperature operation. Conventional and GC SOI have similar third order harmonic distortion in all studied temperatures.Artigo de evento 0 Citação(ões) na Scopus A charge-based continuous model for small-geometry graded-channel SOI MOSFET's(2005-09-07) Michelly De Souza; Marcelo Antonio PavanelloIn this work a continuous model for analog simulation of short-channel Graded-Channel (GC) Silicon-On-Insulator (SOI) nMOSFET is presented. Effects of channel length modulation and velocity saturation have been included in the model formulation, which is based on the series combination of two conventional SOI nMOSFETs, each one representing one of the regions of GC SOI MOSFET channel and its characteristics. Experimental results and numerical bidimensional simulations are used to validate the model with excellent agreement in both cases.- High performance analog operation of double gate transistors with the graded-channel architecture at low temperatures(2005) Pavanello M.A.; Martino J.A.; Raskin J.-P.; Flandre D.This work studies the use of channel engineering by means of graded-channel profile on double gate SOI MOSFETs for improving the analog performance and comparing their output characteristics with conventional double gate SOI transistors at low temperatures from room temperature down to 95 K. Two-dimensional simulations performed here provide a physical explanation for the improved analog device characteristics given by the double gate graded-channel MOSFETs, showing significantly reduced electric field and hence impact ionization rate, which is well known to plague the output characteristics of SOI MOSFETs in the low temperature range. The Early voltage degrades as the temperature decreases but this reduction reflects negligibly in the low frequency open loop gain for a temperature range of 150-300 K due to compensation provided by the transconductance over drain current ratio. The graded-channel structure can finally improve the intrinsic gain of conventional double gate transistor from 67 dB to 90 dB at 300 K. In the range of L LD/L between 0.20 and 0.35, the gain reaches 90 dB and is weakly temperature-dependent with less than 10% reduction in the range of 300 K down to 95 K. © 2005 Elsevier Ltd. All rights reserved.