Departamento de Física
URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/785
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17 resultados
Resultados da Pesquisa
- Reliability-Performance Analysis of Hardware and Software Co-Designs in SRAM-Based APSoCs(2018) Tambara L.A.; Kastensmidt F.L.; Rech P.; Lins F.; Medina N.H.; Added N.; Aguiar V.A.P.; Silveira M.A.G.© 1963-2012 IEEE.All programmable system-on-chip (APSoC) devices provide higher system performance and programmable flexibility at lower costs compared to standalone field-programmable gate array devices and processors. Unfortunately, it has been demonstrated that the high complexity and density of APSoCs increase the system's susceptibility to radiation-induced errors. This paper investigates the effects of soft errors on APSoCs at design level through reliability and performance analyses. We explore 28 different hardware and software co-designs varying the workload distribution between hardware and software. We also propose a reliability analysis flow based on fault injection (FI) to estimate the reliability trend of hardware-only and software-only designs and hardware-software co-designs. Results obtained from both radiation experiments and FI campaigns reveal that performance and reliability can be improved up to 117× by offloading the workload of an APSoC-based system to its programmable logic core. We also show that the proposed flow is a precise method to estimate the reliability trend of system designs on APSoCs before radiation experiments.
- Analyzing the Influence of the Angles of Incidence and Rotation on MBU Events Induced by Low LET Heavy Ions in a 28-nm SRAM-Based FPGA(2017) Tonfat J.; Kastensmidt F.L.; Artola L.; Hubert G.; Medina N.H.; Added N.; Aguiar V.A.P.; Aguirre F.; Macchione E.L.A.; Silveira M.A.G.© 1963-2012 IEEE.This paper shows the impact of low linear energy transfer heavy ions on the reliability of 28-nm Bulk static random access memory (RAM) cells from Artix-7 field-programmable gate array. Irradiation tests on the ground showed significant differences in the multiple bit upset cross section of configuration RAM and block RAM memory cells under various angles of incidence and rotation of the device. Experimental data are analyzed at transistor level by using the single-event effect prediction tool called multiscale single-event phenomenon prediction platform coupled with SPICE simulations.
- Electronic stopping power of Ti, V and Cr ions in Ge and Au at 150–500 keV/u energies(2017) Linares R.; Ribas R.V.; Oliveira J.R.B.; Medina N.H.; Santos H.C.; Seabra C.C.; Sigaud L.; Cybulska E.W.; Seale W.A.; Allegro P.R.P.; Touffen D.L.; Silveira M.A.G.© 2017 Elsevier B.V.In this paper new experimental data are presented for the stopping power of Ti, V and Cr ions in Ge and Au, in the 150–500 keV/u energy range. The heavy ions at low energies are produced from the elastic scattering between particles of an energetic primary beam (28Si and 16O) directed onto the primary foil of interest (Ti, V or Cr). Measurements were performed using the transmission method. New experimental data points for the stopping power of Ti in Au were compared with previous measurement. The agreement between these two datasets indicates the consistence of the experimental technique. Our experimental data were also compared to some selected theoretical and semi-empirical methods: i) the Unitary Convolution Approximation, ii) the Binary theory, iii) the SRIM code and iv) the Northcliffe & Schilling tables. The experimental data for Ge foil deviate from the theoretical curves possibly due to the effect of band gap structure of the material in the electronic stopping power. For the systems measured here, we observe that the Binary theory exhibits an overall good agreement. The velocity-proportional dependence of the electronic stopping power in the measured energy range is also discussed.
- Analyzing Reliability and Performance Trade-Offs of HLS-Based Designs in SRAM-Based FPGAs under Soft Errors(2017) Tambara L.A.; Tonfat J.; Santos A.; Kastensmidt F.L.; Medina N.H.; Added N.; Aguiar V.A.P.; Aguirre F.; Silveira M.A.G.© 1963-2012 IEEE.The increasing system complexity of FPGA-based hardware designs and shortening of time-to-market have motivated the adoption of new designing methodologies focused on addressing the current need for high-performance circuits. High-Level Synthesis (HLS) tools can generate Register Transfer Level (RTL) designs from high-level software programming languages. These tools have evolved significantly in recent years, providing optimized RTL designs, which can serve the needs of safety-critical applications that require both high performance and high reliability levels. However, a reliability evaluation of HLS-based designs under soft errors has not yet been presented. In this work, the trade-offs of different HLS-based designs in terms of reliability, resource utilization, and performance are investigated by analyzing their behavior under soft errors and comparing them to a standard processor-based implementation in an SRAM-based FPGA. Results obtained from fault injection campaigns and radiation experiments show that it is possible to increase the performance of a processor-based system up to 5,000 times by changing its architecture with a small impact in the cross section (increasing up to 8 times), and still increasing the Mean Workload Between Failures (MWBF) of the system.
- Analysis of SRAM-Based FPGA SEU Sensitivity to Combined EMI and TID-Imprinted Effects(2016) Benfica J.; Green B.; Porcher B.C.; Poehls L.B.; Vargas F.; Medina N.H.; Added N.; De Aguiar V.A.P.; Macchione E.L.A.; Aguirre F.; Silveira M.A.G.; Perez M.; Sofo Haro M.; Sidelnik I.; Blostein J.; Lipovetzky J.; Bezerra E.A.© 2016 IEEE.This work proposes a novel methodology to evaluate SRAM-based FPGA's susceptibility with respect to Single-Event Upset (SEU) as a function of noise on VDD power pins, Total-Ionizing Dose (TID) and TID-imprinted effect on BlockRAM cells. The proposed procedure is demonstrated for SEU measurements on a Xilinx Spartan 3E FPGA operating in an 8 MV Pelletron accelerator for the SEU test with heavy-ions, whereas TID was deposited by means of a Shimadzu XRD-7000 X-ray diffractometer. In order to observe the TID-induced imprint effect inside the BlockRAM cells, a second SEU test with neutrons was performed with Americium/Beryllium (241 AmBe). The noise was injected into the power supply bus according to the IEC 61.000-4-29 standard and consisted of voltage dips with 16.67% and 25% of the FPGA's VDD at frequencies of 10 Hz and 5 kHz, respectively. At the end of the experiment, the combined SEU failure rate, given in error/bit.day, is calculated for the FPGA's BlockRAM cells. The combined failure rate is defined as the average SEU failure rate computed before and after exposition of the FPGA to the TID.
- A commercial off-the-shelf pMOS transistor as X-ray and heavy ion detector(2015) Silveira M.A.G.; Melo M.A.A.; Aguiar V.A.P.; Rallo A.; Santos R.B.B.; Medina N.H.; Added N.; Seixas L.E.; Leite F.G.; Cunha F.G.; Cirne K.H.; Giacomini R.; de OLIVEIRA J.A.© Published under licence by IOP Publishing Ltd.Recently, p-channel metal-oxide-semiconductor (pMOS) transistors were suggested as fit for the task of detecting and quantifying ionizing radiation dose. Linearity, small detection volume, fast readout, portability, low power consumption and low radiation attenuation are some of the pMOS advantages over PIN diode and thermoluminiscent dosimeters. A hand-held measurement system using a low power commercial off-the-shelf pMOSas the sensor would have a clear advantage due to the lower cost incurred by a standard technological process. In this research work, we tested the commercial device 3N163 regarding its behaviouras an X-ray sensor, as well as its possible application as a heavy-ion detector. To study the radiation effects of X-rays, a XRD-7000 (Shimadzu) X-ray diffraction setup was used to produce 10-keV effective energy photons. Heavy ions tests involved 12C, 16O, 19F, 28Si, 35Cl, 63Cu and 107Ag beams scattered at 15° by a 275 μg/cm2 gold target, which provide LETs (Linear Energy Transfer) from 4 to 40 MeV/mg/cm2. The signal readout was done using a 1 GHz oscilloscope with a 10-Gsamples/s conversion rate, high enough to permit the recording of transient pulses in the drain current. In this case, an ion can cause a current signal proportional to the ion beam used. Through this study it was found that a simple commercial pMOS device can be reliably used as a detector of X-rays as well as heavy ion detector.
- Using the wave layout style to boost the digital ICs electrical performance in the radioactive environment(2015) Navarenho-De-Souza R.; Silveira M.A.G.; Gimenez S.P.© The Electrochemical Society.This paper presents an experimental comparative study between the Metal-Oxide-Semiconductor Field Effect Transistors (MOSFET) manufactured with the Wave ("S" gate geometry) and the standard layout (CnM) considering the Total Ionizing Dose (TID) effects and taking into account that the devices were biased during the radiation procedure to emphasize the effects. Due to the special layout characteristics and the different effects of the bird's beaks regions of the Wave MOSFET (WnM) compared to the conventional rectangular layout, this innovative layout proposal for MOSFETs is able to improve the device TID tolerance without adding cost to the Complementary MOS (CMOS) manufacturing process.
- Analog performance of standard and uniaxial strained triple-gate SOI FinFETs under x-ray radiation(2014) Bordallo C.C.M.; Teixeira F.F.; Silveira M.A.G.; Martino J.A.; Agopian P.G.D.; Simoen E.; Claeys C.© 2014 IOP Publishing Ltd.The influence of x-ray irradiation on the main digital and analog parameters of triple gate silicon-on- insulator FinFETs is investigated for unstrained and uniaxially strained devices. Comparing the p- and n-MuGFET response to radiation, x-rays can be more harmful for nMuGFETs than for the p-type counterparts due to the back-interface leakage current, which is generated by the positive charges trapped in the buried oxide. However, in pMuGFETs, the radiation tends to suppress the parasitic back-conduction, resulting in an improvement of the device performance.
- A system to measure isomeric state half-lives in the 10 ns to 10 μs range(2014) Toufen D.L.; Allegro P.R.P.; Medina N.H.; Oliveira J.R.B.; Cybulska E.W.; Seale W.A.; Linares R.; Silveira M.A.G.; Ribas R.V.The Isomeric State Measurement System (SISMEI) was developed to search for isomeric nuclear states produced by fusion-evaporation reactions. The SISMEI consists of 10 plastic phoswich telescopes, two lead shields, one NaI(Tl) scintillation detector, two Compton suppressed HPGe γ-ray detectors, and a cone with a recoil product catcher. The new system was tested at the 8 UD Pelletron tandem accelerator of the University of São Paulo with the measurement of two known isomeric states: 54Fe, 10+ state (E = 6527.1 (11) keV, T1/2 = 364(7) ns) and the 5/2+ state of 19F (E = 197.143 (4) keV, T1/2 = 89.3 (10) ns). The results indicate that the system is capable of identifying delayed transitions, of measuring isomeric state lifetimes, and of identifying the feeding transitions of the isomeric state through the delayed γ-γ coincidence method. The measured half-life for the 10+ state was T1/2 = 365(14) ns and for the 5/2+ state, 100(36) ns. © 2014 AIP Publishing LLC.
- Reliability on ARM Processors Against Soft Errors Through SIHFT Techniques(2016) Chielle E.; Rosa F.; Rodrigues G.S.; Tambara L.A.; Tonfat J.; Macchione E.; Aguirre F.; Added N.; Medina N.; Aguiar V.; Silveira M.A.G.; Ost L.; Reis R.; Cuenca-Asensi S.; Kastensmidt F.L.© 1963-2012 IEEE.ARM processors are leaders in embedded systems, delivering high-performance computing, power efficiency, and reduced cost. For this reason, there is a relevant interest for its use in the aerospace industry. However, the use of sub-micron technologies has increased the sensitivity to radiation-induced transient faults. Thus, the mitigation of soft errors has become a major concern. Software-Implemented Hardware Fault Tolerance (SIHFT) techniques are a low-cost way to protect processors against soft errors. On the other hand, they cause high overheads in the execution time and memory, which consequently increase the energy consumption. In this work, we implement a set of software techniques based on different redundancy and checking rules. Furthermore, a low-overhead technique to protect the program execution flow is included. Tests are performed using the ARM Cortex-A9 processor. Simulated fault injection campaigns and radiation test with heavy ions have been performed. Results evaluate the trade-offs among fault detection, execution time, and memory footprint. They show significant improvements of the overheads when compared to previously reported techniques.