Please use this identifier to cite or link to this item: https://repositorio.fei.edu.br/handle/FEI/1097
Title: Surface Potential-Based Drain Current Analytical Model for Triple-Gate Junctionless Nanowire Transistors
Authors: TREVISOLI, R D
DORIA, R. T.
DE SOUZA, Michelly
DAS, Samaresh
FERAIN, I.
PAVANELLO, Marcelo A.
Issue Date: 2012
Journal: IEEE Transactions on Electron Devices
ISSN: 0018-9383
Citation: TREVISOLI, R D; DORIA, R. T.; DE SOUZA, Michelly; DAS, Samaresh; FERAIN, I.; PAVANELLO, Marcelo A.. Surface Potential-Based Drain Current Analytical Model for Triple-Gate Junctionless Nanowire Transistors. IEEE Transactions on Electron Devices, v. 59, n. 12, p. 3510-3518, 2012.
Access Type: Acesso Aberto
DOI: 10.1109/TEd.2012.2219055
URI: https://repositorio.fei.edu.br/handle/FEI/1097
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