Analysis of the substrate bias effect on the interface trapped charges in junctionless nanowire transistors through low-frequency noise characterization
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10
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2017
Autores
Doria R.T.
Trevisoli R.
de Souza M.
Barraud S.
Vinet M.
Faynot O.
Pavanello M.A.
Trevisoli R.
de Souza M.
Barraud S.
Vinet M.
Faynot O.
Pavanello M.A.
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Periódico
Microelectronic Engineering
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DORIA, Rodrigo Trevisoli; TREVISOLI, Renan D.; DE SOUZA, Michelly; VINET, MAUD; BARRAUD, SYLVAIN; PAVANELLO, Marcelo A.. Analysis of the substrate bias effect on the interface trapped charges in junctionless nanowire transistors through low-frequency noise characterization. MICROELECTRONIC ENGINEERING, v. 178, p. 17-20, 2017.
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© 2017 Elsevier B.V.This work presents, for the first time, an experimental analysis of the low-frequency noise and the effective trap density dependence of junctionless nanowire transistors (JNTs) on the substrate bias. The study has been performed for devices with different channel lengths and doping concentrations biased close to the threshold and deep in linear regime. It has been shown that the surface potential of JNTs is strongly influenced by the substrate bias even above threshold. Thus, the drain current noise spectral density and the effective trap density can be improved or degraded depending on the bias applied to the substrate of the devices. Additionally, it is shown that, the variation on the substrate bias enables the evaluation of traps with different activation energy ranges, which is more evident in heavier doped devices due to the higher threshold voltage sensitivity to the substrate bias.