Please use this identifier to cite or link to this item: https://repositorio.fei.edu.br/handle/FEI/1141
Title: Modeling the interface traps-related low frequency noise in triple-gate SOI junctionless nanowire transistors
Authors: TREVISOLI, RENAN
Doria, Rodrigo Trevisoli
BARRAUD, SYLVAIN
Pavanello, Marcelo Antonio
Issue Date: 2019
Journal: MICROELECTRONIC ENGINEERING
ISSN: 0167-9317
Citation: TREVISOLI, RENAN; Doria, Rodrigo Trevisoli; BARRAUD, SYLVAIN; Pavanello, Marcelo Antonio. Modeling the interface traps-related low frequency noise in triple-gate SOI junctionless nanowire transistors. MICROELECTRONIC ENGINEERING, v. 215, p. 111005, 2019.
Access Type: Acesso Aberto
DOI: 10.1016/j.mee.2019.111005
URI: https://repositorio.fei.edu.br/handle/FEI/1141
Appears in Collections:Artigos

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