New method for individual electrical characterization of stacked SOI nanowire MOSFETs
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4
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2017-10-18
Autores
PAZ, B.C.
CASSE, M.
BARRAUD, S.
REIMBOLD, G.
VINET, M.
FAYNOT, O.
Marcelo Antonio Pavanello
CASSE, M.
BARRAUD, S.
REIMBOLD, G.
VINET, M.
FAYNOT, O.
Marcelo Antonio Pavanello
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Periódico
2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017
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PAZ, B.C.; CASSE, M.; BARRAUD, S.; REIMBOLD, G.; VINET, M.; FAYNOT, O.; PAVANELLO, M. A. New method for individual electrical characterization of stacked SOI nanowire MOSFETs. 2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017, p.1-3, 2018.
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A new systematic procedure to separate the electrical characteristics of advanced stacked nanowires (NWs) with emphasis on mobility extraction is presented. The proposed method is based on I-V measurements varying the back gate bias (VB) and consists of three basic main steps, accounting for VB influence on transport parameters. Lower mobility was obtained for the top GAA NW in comparison to bottom Q-NW. Temperature dependence of carrier mobility is also studied through the proposed method up to 150°C.