Performance and transport analysis of vertically stacked p-FET SOI nanowires
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4
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2017-06-29
Autores
PAZ, B. C.
Marcelo Antonio Pavanello
CASSE, M.
BARRAUD, S.
REIMBOLD, G.
VINET, M.
FAYNOT, O.
Marcelo Antonio Pavanello
CASSE, M.
BARRAUD, S.
REIMBOLD, G.
VINET, M.
FAYNOT, O.
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Joint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017 - Proceedings
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PAZ, B. C.; PAVANELLO, M. A.; CASSE, M.; BARRAUD, S.; REIMBOLD, G.; VINET, M.; FAYNOT, O. Performance and transport analysis of vertically stacked p-FET SOI nanowires. Joint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017 - Proceedings, p. 79-82, jun. 2017.
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This work presents the performance and transport characteristics of vertically stacked p-MOSFET SOI nanowires (NWs) with inner spacers and epitaxial growth of SiGe raised source/drain. Electrical characterization is performed for NWs with [110] and [100] channel orientations, as a function of both fin width (WFIN) and channel length (L). Results show a good electrostatic control and reduced short channel effects (SCE) down to 15nm gate length. Improved effective mobility is obtained for [110]-oriented NWs due to higher sidewall mobility contribution.