Analog performance improvement of self-cascode structures composed by UTBB transistors using back gate bias
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6
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2015-11-20
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Rodrido Doria
TREVISOLI, R.
Michelly De Souza
Marcelo Antonio Pavanello
FLANDRE, D.
TREVISOLI, R.
Michelly De Souza
Marcelo Antonio Pavanello
FLANDRE, D.
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2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015
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DORIA, R.; TREVISOLI, R.; DE SOUZA, M.; PAVANELLO, M. A. Analog performance improvement of self-cascode structures composed by UTBB transistors using back gate bias. 2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015. Nov. 2015.
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This paper explores the use of the back gate bias to enhance the analog performance of self-cascode structures composed by 25nm-long UTBB SOI MOSFETs. It is shown, for the first time, that the use of back gate bias can improve the intrinsic voltage gain by 15 dB, making it larger than the one presented by a 50nm-long single device.