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Impact of Using the Octagonal Layout for SOI MOSFETs in a High-Temperature Environment

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Tipo de produção

Artigo

Data de publicação

2015

Texto completo (DOI)

Periódico

IEEE Transactions on Device and Materials Reliability

Editor

Citações na Scopus

12

Autores

Gimenez S.P.
Galembeck E.H.S.
Renaux C.
Flandre D.

Orientadores

Resumo

© 2015 IEEE.The impact of high-temperature effects is experimentally investigated in the octagonal layout style for planar silicon-on-insulator (SOI) metal-oxide-semiconductor (MOS) field-effect transistors (MOSFETs), named OCTO SOI MOSFETs (OSMs), in relation to the hexagonal [diamond SOI MOSFETs (DSMs)] and the standard (rectangular conventional SOI MOSFETs) ones regarding the same bias conditions. The devices were manufactured with a 1-μ m fully depleted SOI complementary MOS (CMOS) technology. The main experimental findings demonstrate that OSM is capable of keeping active the longitudinal corner effect and the PArallel connection of MOSFET with Different channel Lengths Effect (PAMDLE) in its structure at high-temperature conditions, and consequently, it maintains its remarkably better electrical performance in comparison with the standard SOI MOSFET, mainly its capacity to reduce the leakage drain current, without causing any extra burden to the current planar SOI CMOS technology in relation to DSMs.

Citação

GIMENEZ, S. P.; GALEMBECK, E. H. S.; RENAUX, CHRISTIAN; FLANDRE, D. Impact of Using the Octagonal Layout for SOI MOSFETs in High Temperature Environment. IEEE Transactions on Device and Materials Reliability, v. 99, n. 1, p. 1-1, 2015.

Palavras-chave

Keywords

high temperature environment; LCE effect and PAMDLE effect; leakage drain current; OCTO layout style

Assuntos Scopus

Electrical performance; High temperature condition; High-temperature environment; LCE effect and PAMDLE effect; Metal oxide semiconductor; OCTO layout style; Parallel connections; Silicon-on- insulators (SOI)

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