Use of back gate bias to enhance the analog performance of planar FD and UTBB SOI transistors-based self-cascode structures

dc.contributor.authorRodrido Doria
dc.contributor.authorFLANDRE, D.
dc.contributor.authorTREVISOLLI, R.
dc.contributor.authorMichelly De Souza
dc.contributor.authorMarcelo Antonio Pavanello
dc.contributor.authorOrcidhttps://orcid.org/0000-0003-1361-3650
dc.contributor.authorOrcidhttps://orcid.org/0000-0001-6472-4807
dc.contributor.authorOrcidhttps://orcid.org/0000-0003-4448-4337
dc.date.accessioned2022-01-12T21:59:45Z
dc.date.available2022-01-12T21:59:45Z
dc.date.issued2015-10-13
dc.description.abstractThis paper reports, for the first time, the use of back gate bias to improve the intrinsic voltage gain of self-cascode structures composed by planar FD and UTBB SOI MOSFETs. It is shown a voltage gain improvement larger than 10 dB when either a forward back bias is applied to the drain-side transistor or a reverse back bias is applied to the source side device.
dc.identifier.citationDORIA, R.; FLANDRE, D.; TREVISOLLI, R.; DE SOUZA, M.; PAVANELLO, M. A. Use of back gate bias to enhance the analog performance of planar FD and UTBB SOI transistors-based self-cascode structures. SBMicro 2015 - 30th Symposium on Microelectronics Technology and Devices. Oct. 2015.
dc.identifier.doi10.1109/SBMicro.2015.7298134
dc.identifier.urihttps://repositorio.fei.edu.br/handle/FEI/3953
dc.relation.ispartofSBMicro 2015 - 30th Symposium on Microelectronics Technology and Devices
dc.rightsAcesso Restrito
dc.subject.otherlanguageSelf-Cascode
dc.subject.otherlanguageSilicon-on-Insulator
dc.subject.otherlanguageUTBB
dc.titleUse of back gate bias to enhance the analog performance of planar FD and UTBB SOI transistors-based self-cascode structures
dc.typeArtigo de evento
fei.scopus.citations4
fei.scopus.eid2-s2.0-84961784558
fei.scopus.subjectAnalog performance
fei.scopus.subjectBack-gate bias
fei.scopus.subjectIntrinsic voltage gains
fei.scopus.subjectReverse back bias
fei.scopus.subjectSelf-cascode
fei.scopus.subjectSOI transistors
fei.scopus.subjectUTBB
fei.scopus.subjectVoltage gain
fei.scopus.updated2024-02-01
fei.scopus.urlhttps://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=84961784558&origin=inward
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