Engenharia Elétrica

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https://repositorio.fei.edu.br/handle/FEI/21

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Navegando Engenharia Elétrica por Autor "Agopian P.G.D."

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    Biaxial + uniaxial stress effectiveness in tri-gate SOI nMOSFETs with variable fin dimensions
    (2012-10-04) BÜHLER, Rudolf Theoderich; Agopian P.G.D.; Simoen E.; Claeys C.; Martino J.A.
    MuGFET devices show good gate-to-channel control, reducing short channel effects and increased current drive [1] and their performance can be improved through implementation of mechanical stress in the silicon fin. In th is wor k we study t he stress distr ibution and transconductance behavior in unstrained and biaxially + uniaxially strained tri-gate SOI nMOSFETs with different fin dimensions through electrical characterization of experimental devices and 3D process and device numerical simulation. Experimental results of standard and strained devices were used to validate the simulations. The bi+uni stress technique delivered enhanced maximum transconductance. © 2012 IEEE.
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    Different stress techniques and their efficiency on triple-gate SOI n-MOSFETs
    (2015) Buhler R.T.; Agopian P.G.D.; Collaert N.; Simoen E.; Claeys C.; Martino J.A.
    © 2014 Elsevier Ltd. All rights reserved.Three techniques to implement mechanical stress in n-channel Multiple Gate MOSFETs (MuGFETs) are investigated through 3D simulations and transconductance measurements. They are: uniaxial stress, biaxial stress and biaxial + uniaxial stress. Four different fin dimensions are evaluated: a narrow and a wide transistor, combined with a short or a long device. It is shown that the stress distribution and the device performance exhibit a dependence on the fin dimensions. For uniaxially strained devices, the dimensions are important as the bending of the silicon required to induce stress in the channel depends on its size. However, for biaxially strained devices the plane of etching in the silicon fin is important, determining the degradation of the stress components. The combination of the two types of stress results in an improvement of some stress components and an overall improvement in the maximum transconductance.
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    Halo optimization for 0.13μm SOI CMOS technology
    (2008) Agopian P.G.D.; Arrabaca J.M.; Martino J.A.
    This work presents the study of HALO implantation angle and its concentration influence on deep-submicrometer partially depleted SOI nMOSFETs electric characteristics. This study was performed through the threshold voltage and subthreshold slope analysis. As the implantation angle and the doping concentration of the HALO were varied, a large threshold voltage variation was obtained. It is demonstrated that for 0.13μm SOI CMOS technology devices, the most efficient HALO implantation occurs for 50 degrees and concentration range from 1.2×1018 cm-3 to 1.8×10 18cm-33. © The Electrochemical Society.