Artigos
URI permanente para esta coleçãohttps://repositorio.fei.edu.br/handle/FEI/798
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Artigo 8 Citação(ões) na Scopus Study of matching properties of graded-channel SOI MOSFETs(2008-01-05) Michelly De Souza; FLANDRE, D.; Marcelo Antonio PavanelloIn this paper an overall analysis on the matching properties of Graded-Channel (GC) SOI MOSFETs in comparison to conventional SOI transistors is performed. Experimental results show that GC devices present poorer matching behavior in comparison to conventional SOI counterpart for equal mask channel length, whereas for same effective channel length, almost the same matching behavior. The analytical model for the drain current of GC devices is used to investigate the reasons for this matching worsening. Two-dimensional numerical simulations are used to validate the model-based analysis both in linear and saturation regions.- Impact of asymmetric channel configuration on the linearity of double-gate SOI MOSFETs(2006-04-26) Marcelo Antonio Pavanello; CERDEIRA, A.; MARTINO, J. A.; RASKIN, J. P.; FLANDRE, D.In this paper the linearity of asymmetric channel double-gate transistors, using the graded-channel (GC) configuration and Gate-All-Around architecture, operating as an amplifier, is studied in terms of lightly doped region length. The total harmonic distortion and third-order harmonic distortion are used as figures of merit. The results are compared with single-gate transistors with similar channel configuration. It is demonstrated that double-gate GC transistors at the same operation region and with similar channel configuration can present up to 20 dB less total harmonic distortion while presenting small third-order harmonic distortion. Considering similar bias voltage, the alternate component of the input sinusoidal signal of GC double-gate devices can be increased by about 200 mV to provide similar third-order harmonic distortion maintaining similar improvements of 20 dB on the total harmonic distortion. © 2006 IEEE.
- Analog performance of asymmetric self-cascode p-channel fully depleted SOI transistors(2012-03-17) Michelly De Souza; Marcelo Antonio Pavanello; FLANDRE, D.This work presents an analysis of the analog performance of asymmetric threshold voltage self-cascode fully depleted (FD) p-type SOI transistors. The experimental results showed that this structure is able to improve the devices transconductance and output conductance, resulting in increased intrinsic voltage gain and breakdown voltage in comparison to single transistors and the conventional symmetric self-cascode. © 2012 IEEE.