Artigos
URI permanente para esta coleçãohttps://repositorio.fei.edu.br/handle/FEI/798
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Resultados da Pesquisa
- Threshold voltages of SOI MuGFETs(2008-12-05) de Andrade M.G.C.; Martino J.A.The multiple-gate field-effect transistor (MuGFET) is a device with a gate folded on different sides of the channel region. They are one of the most promising technological solutions to create high-performance ultra-scaled SOI CMOS. In this work, the behavior of the threshold voltage in double-gate, triple-gate and quadruple-gate SOI transistors with different channel doping concentrations is studied through three-dimensional numerical simulation. The results indicated that for double-gate transistors, one or two threshold voltages can be observed, depending on the channel doping concentration. However, in triple-gate and quadruple-gate it is possible to observe up to four threshold voltages due to the corner effect and the different doping concentration between the top and bottom of the Fin. © 2008 Elsevier Ltd. All rights reserved.
- SOI technology characterization using SOI-MOS capacitor(2005) Sonnenberg V.; Martino J.A.In this paper a set of simple methods is presented, to determine the main parameters of the silicon on insulator technology, using a thin film SOI-MOS capacitor. Methods to obtain the effective substrate doping concentration, substrate interface charge density and the buried oxide thickness using the two terminal SOI capacitor are presented. The front gate oxide thickness, the silicon film thickness, the silicon doping concentration and front and back interface charge density are obtained using a three terminal SOI-MOS capacitor. Bidimensional numerical simulations of SOI structure are performed for analyzing the high frequency capacitance vs. voltage curves and to test the proposed methods. These methods were applied experimentally and coherent results were found. © 2004 Elsevier Ltd. All rights reserved.
- Different stress techniques and their efficiency on triple-gate SOI n-MOSFETs(2015) Buhler R.T.; Agopian P.G.D.; Collaert N.; Simoen E.; Claeys C.; Martino J.A.© 2014 Elsevier Ltd. All rights reserved.Three techniques to implement mechanical stress in n-channel Multiple Gate MOSFETs (MuGFETs) are investigated through 3D simulations and transconductance measurements. They are: uniaxial stress, biaxial stress and biaxial + uniaxial stress. Four different fin dimensions are evaluated: a narrow and a wide transistor, combined with a short or a long device. It is shown that the stress distribution and the device performance exhibit a dependence on the fin dimensions. For uniaxially strained devices, the dimensions are important as the bending of the silicon required to induce stress in the channel depends on its size. However, for biaxially strained devices the plane of etching in the silicon fin is important, determining the degradation of the stress components. The combination of the two types of stress results in an improvement of some stress components and an overall improvement in the maximum transconductance.
- A simple current model for edgeless SOI nMOSFET and a 3-D analysis(2005) Giacomini R.; Martino J.A.This work presents a new approach for the current model of thin-film, fully depleted SOI edgeless transistors, based on the asymmetric trapezoidal gate model. The most common current model for an edgeless transistor is obtained by taking the rectangular device drain current expression and substituting the device width by an "equivalent" device width, usually given by the average between source and drain width of the channel. However, this model does not take into account some effects that take place near the corners of the device and that have a significant influence on the current expression. The new model is tested using three-dimensional numerical simulation and experimental data. The proposed model is still simple and both simulation and experimental results show that it presents an improved performance. © 2005 Elsevier Ltd. All rights reserved.
- Low-frequency noise of n-type triple gate FinFETs fabricated on standard and 45 rotated substrates(2013) Doria R.T.; Martino J.A.; Simoen E.; Claeys C.; Pavanello M.A.This paper studies the impact of the 45 substrate rotation on the low-frequency noise (LFN) of triple gate nFinFETs. The overall LFN has been extracted for both standard and 45 substrate rotated devices of several fin widths at different drain and gate voltage biases focusing on their operation in saturation regime. A general view of the mechanisms which govern the low-frequency noise in MOS devices is provided and a brief discussion on the physical origins of the LFN in the evaluated devices is carried out. It has been noted that the LFN in non-rotated (0 rotated) and 45 rotated devices operating in the linear regime shows 1/f behavior independent on the gate bias, whereas in the saturation regime both 1/f and Lorentzian (1/f2) noises are observed. The former one prevails at lower frequencies and the 1/f2 noise at higher ones. In this case, the corner frequency shows an exponential dependence on the gate bias. © 2013 Elsevier Ltd. All rights reserved.
- Analysis of temperature variation influence on the analog performance of 45° rotated triple-gate nMuGFETs(2012) Pavanello M.A.; Souza M.D.; Martino J.A.; Simoen E.; Claeys C.This work presents the analog performance of n-type triple-gate MuGFETs with high-k dielectrics and TiN gate material fabricated in 45° rotated SOI substrates comparing their performance with standard MuGFETs fabricated without substrate rotation. Different fin widths are studied for temperatures ranging from 250 K up to 400 K. The results of transconductance, output conductance, transconductance over drain current ratio, intrinsic voltage gain and unit-gain frequency are studied. It is observed that the substrate rotation improves the carrier mobility of narrow MuGFETs at any temperature because of the changing in the conduction plane at the sidewalls from (1 1 0) to (1 0 0). For lower temperatures, the improvement of the carrier mobility of rotated MuGFETs is more noticeable as well as the rate of mobility improvement with the temperature decrease is larger. The output conductance is weakly affected by the substrate rotation. Although this improvement in the transconductance of rotated MuGFETs is negligibly transferred to the intrinsic voltage gain, the unity-gain frequency of rotated device is improved due to the larger carrier mobility in the entire range of temperatures studied. © 2011 Elsevier Ltd. All rights reserved.
- Analog performance of standard and strained triple-gate silicon-on-insulator nFinFETs(2008) Pavanello M.A.; Martino J.A.; Simoen E.; Rooyackers R.; Collaert N.; Claeys C.This work shows a comparison between the analog performance of standard and strained Si n-type triple-gate FinFETs with high-κ dielectrics and TiN gate material. Different channel lengths and fin widths are studied. It is demonstrated that both standard and strained FinFETs with short channel length and narrow fins have similar analog properties, whereas the increase of the channel length degrades the early voltage of the strained devices, consequently decreasing the device intrinsic voltage gain with respect to standard ones. Narrow strained FinFETs with long channel show a degradation of the Early voltage if compared to standard ones suggesting that strained devices are more subjected to the channel length modulation effect. © 2008 Elsevier Ltd. All rights reserved.
- Harmonic distortion of 2-MOS structures for MOSFET-C filters implemented with n-type unstrained and strained FINFETS(2011) Doria R.T.; Simoen E.; Claeys C.; Martino J.A.; Pavanello M.A.This work investigates the harmonic distortion (HD) in 2-MOS balanced structures composed of triple gate FinFETs. HD has been evaluated through the determination of the third-order harmonic distortion (HD3), since this represents the major non-linearity source in balanced structures. The 2-MOS structures with devices of different channel lengths (L) and fin widths (W fin) have been studied operating in the linear region as tunable resistors. The analysis was performed as a function of the gate voltage, aiming to verify the correlation between operation bias and HD3. The physical origins of the non-linearities have been investigated and are pointed out. Being a resistive circuit, the 2-MOS structure is generally projected for a targeted on-resistance, which has also been evaluated in terms of HD3. The impact of the application of biaxial strain has been studied for FinFETs of different dimensions. It has been noted that HD3 reduces with the increase of the gate bias for all the devices and this reduction is more pronounced both in narrower and in longer devices. Also, the presence of strain slightly diminishes the non-linearity at a similar bias. However, a drawback associated with the use of strain engineering consists in a significant reduction of the on-resistance with respect to unstrained devices. © 2011 Elsevier Ltd. All rights reserved.
- Analysis of uniaxial and biaxial strain impact on the linearity of fully depleted SOI nMOSFETs(2007) Pavanello M.A.; Martino J.A.; Simoen E.; Claeys C.This work studies the impact of uniaxial, biaxial and combined uniaxial-biaxial strain on the linearity of nMOSFETs from a 65 nm fully depleted (FD) SOI technology. The total harmonic distortion (THD) and third-order harmonic distortion (HD3) will be used as figures of merit. Operation in saturation and triode regimes will be the focus. When biased in the saturation region short-channel devices have been used and biased as single-transistor amplifiers. In this case, at low voltage bias the use of any kind of strain improves the THD in comparison to standard SOI. When operating in linear region as a quasi-linear resistor longer devices were studied. For operation in linear regime the HD3 is nearly the same for all devices and no clear strain influence can be found at similar bias condition. If a target on-resistance is considered, the use of biaxially or combined unxially-biaxially strained films can provide a reduction on the required gate voltage overdrive or a reduction on the device channel width without degrading the HD3. © 2007 Elsevier Ltd. All rights reserved.
- Impact of halo implantation on 0.13 μm floating body partially depleted SOI n-MOSFETs in low temperature operation(2005) Pavanello M.A.; Martino J.A.; Simoen E.; Claeys C.This work studies the effect of halo implantation on the electrical characteristics of deep-submicrometer partially depleted SOI nMOSFETs during low temperature and floating body operation. Parameters such as the drain induced barrier lowering (DIBL) and the device thermal resistance have been investigated. It is shown that the combination of floating body operation with halo implantation degrades the DIBL in the temperature range studied (90 K-300 K) in comparison to devices that did not received this implantation. The halo region causes a more pronounced negative output conductance than for the transistors without a halo implantation. An estimation of the temperature rise for a given dissipated power in both types of devices is made, based on the thermal resistance, which is derived from the output characteristics in function of the temperature. © 2005 Elsevier Ltd. All rights reserved.