Artigos
URI permanente para esta coleçãohttps://repositorio.fei.edu.br/handle/FEI/798
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27 resultados
Resultados da Pesquisa
- Threshold voltages of SOI MuGFETs(2008-12-05) de Andrade M.G.C.; Martino J.A.The multiple-gate field-effect transistor (MuGFET) is a device with a gate folded on different sides of the channel region. They are one of the most promising technological solutions to create high-performance ultra-scaled SOI CMOS. In this work, the behavior of the threshold voltage in double-gate, triple-gate and quadruple-gate SOI transistors with different channel doping concentrations is studied through three-dimensional numerical simulation. The results indicated that for double-gate transistors, one or two threshold voltages can be observed, depending on the channel doping concentration. However, in triple-gate and quadruple-gate it is possible to observe up to four threshold voltages due to the corner effect and the different doping concentration between the top and bottom of the Fin. © 2008 Elsevier Ltd. All rights reserved.
- Halo optimization for 0.13μm SOI CMOS technology(2008) Agopian P.G.D.; Arrabaca J.M.; Martino J.A.This work presents the study of HALO implantation angle and its concentration influence on deep-submicrometer partially depleted SOI nMOSFETs electric characteristics. This study was performed through the threshold voltage and subthreshold slope analysis. As the implantation angle and the doping concentration of the HALO were varied, a large threshold voltage variation was obtained. It is demonstrated that for 0.13μm SOI CMOS technology devices, the most efficient HALO implantation occurs for 50 degrees and concentration range from 1.2×1018 cm-3 to 1.8×10 18cm-33. © The Electrochemical Society.
- Biaxial + uniaxial stress effectiveness in tri-gate SOI nMOSFETs with variable fin dimensions(2012-10-04) BÜHLER, Rudolf Theoderich; Agopian P.G.D.; Simoen E.; Claeys C.; Martino J.A.MuGFET devices show good gate-to-channel control, reducing short channel effects and increased current drive [1] and their performance can be improved through implementation of mechanical stress in the silicon fin. In th is wor k we study t he stress distr ibution and transconductance behavior in unstrained and biaxially + uniaxially strained tri-gate SOI nMOSFETs with different fin dimensions through electrical characterization of experimental devices and 3D process and device numerical simulation. Experimental results of standard and strained devices were used to validate the simulations. The bi+uni stress technique delivered enhanced maximum transconductance. © 2012 IEEE.
- SOI technology characterization using SOI-MOS capacitor(2005) Sonnenberg V.; Martino J.A.In this paper a set of simple methods is presented, to determine the main parameters of the silicon on insulator technology, using a thin film SOI-MOS capacitor. Methods to obtain the effective substrate doping concentration, substrate interface charge density and the buried oxide thickness using the two terminal SOI capacitor are presented. The front gate oxide thickness, the silicon film thickness, the silicon doping concentration and front and back interface charge density are obtained using a three terminal SOI-MOS capacitor. Bidimensional numerical simulations of SOI structure are performed for analyzing the high frequency capacitance vs. voltage curves and to test the proposed methods. These methods were applied experimentally and coherent results were found. © 2004 Elsevier Ltd. All rights reserved.
- Different stress techniques and their efficiency on triple-gate SOI n-MOSFETs(2015) Buhler R.T.; Agopian P.G.D.; Collaert N.; Simoen E.; Claeys C.; Martino J.A.© 2014 Elsevier Ltd. All rights reserved.Three techniques to implement mechanical stress in n-channel Multiple Gate MOSFETs (MuGFETs) are investigated through 3D simulations and transconductance measurements. They are: uniaxial stress, biaxial stress and biaxial + uniaxial stress. Four different fin dimensions are evaluated: a narrow and a wide transistor, combined with a short or a long device. It is shown that the stress distribution and the device performance exhibit a dependence on the fin dimensions. For uniaxially strained devices, the dimensions are important as the bending of the silicon required to induce stress in the channel depends on its size. However, for biaxially strained devices the plane of etching in the silicon fin is important, determining the degradation of the stress components. The combination of the two types of stress results in an improvement of some stress components and an overall improvement in the maximum transconductance.
- Modeling silicon on insulator MOS transistors with nonrectangular-gate layouts(2006) Giacomini R.; Martino J.A.This work presents a new and simple approach for modeling silicon on insulator metal-oxide-semiconductor (MOS) dc characteristics for nonrectangular layout devices, based on decomposition of the original shape into trapezoidal parts and on an accurate but simple model of the trapezoidal layout transistor. Analytical expressions relating geometrical parameters and terminal current and voltages are presented for several shapes, such as L, U, T, and S, and other well-known devices such as the edgeless transistor and the asymmetric trapezoidal gate transistor. The proposed closed-form analytical expressions show good agreement with measured data and three-dimensional simulation results. © 2006 The Electrochemical Society. All rights reserved.
- Trapezoidal cross-sectional influence on FinFET threshold voltage and corner effects(2008) Giacomini R.; Martino J.A.Fin field effect transistors (FinFETS) are silicon-on-insulator (SOI) transistors with three-dimensional structures. As a result of some fabrication-process limitations (as nonideal anisotropic overetch) some FinFETs have inclined surfaces, which results in trapezoidal cross sections instead of rectangular sections, as expected. This geometric alteration results in some device issues, like carrier profile, threshold voltage, and corner effects. This work analyzes these consequences based on three-dimensional numeric simulation of several dual-gate and triple-gate FinFETs. The simulation results show that the threshold voltage depends on the sidewall inclination angle and that this dependence varies according to the body doping level. The corner effects also depend on the inclination angle and doping level. © 2008 The Electrochemical Society.
- A simple current model for edgeless SOI nMOSFET and a 3-D analysis(2005) Giacomini R.; Martino J.A.This work presents a new approach for the current model of thin-film, fully depleted SOI edgeless transistors, based on the asymmetric trapezoidal gate model. The most common current model for an edgeless transistor is obtained by taking the rectangular device drain current expression and substituting the device width by an "equivalent" device width, usually given by the average between source and drain width of the channel. However, this model does not take into account some effects that take place near the corners of the device and that have a significant influence on the current expression. The new model is tested using three-dimensional numerical simulation and experimental data. The proposed model is still simple and both simulation and experimental results show that it presents an improved performance. © 2005 Elsevier Ltd. All rights reserved.
- An analytic method to compute the stress dependence on the dimensions and its influence in the characteristics of triple gate devices(2012) Trevisoli R.D.; Martino J.A.; Simoen E.; Claeys C.; Pavanello M.A.Triple-gate devices are considered a promising solution for sub-20 nm era. Strain engineering has also been recognized as an alternative due to the increase in the carriers mobility it propitiates. The simulation of strained devices has the major drawback of the stress non-uniformity, which cannot be easily considered in a device TCAD simulation without the coupled process simulation that is time consuming and cumbersome task. However, it is mandatory to have accurate device simulation, with good correlation with experimental results of strained devices, allowing for in-depth physical insight as well as prediction on the stress impact on the device electrical characteristics. This work proposes the use of an analytic function, based on the literature, to describe accurately the strain dependence on both channel length and fin width in order to simulate adequately strained triple-gate devices. The maximum transconductance and the threshold voltage are used as the key parameters to compare simulated and experimental data. The results show the agreement of the proposed analytic function with the experimental results. Also, an analysis on the threshold voltage variation is carried out, showing that the stress affects the dependence of the threshold voltage on the temperature. © 2011 Elsevier Ltd. All rights reserved.
- Improved operation of graded-channel SOI nMOSFETs down to liquid helium temperature(2016) Pavanello M.A.; De Souza M.; Ribeiro T.A.; Martino J.A.; Flandre D.© 2016 IOP Publishing Ltd.This paper presents the operation of Graded-Channel (GC) Silicon-On-Insulator (SOI) nMOSFETs at low temperatures down to liquid helium temperature in comparison to standard uniformly doped transistors. Devices from two different technologies have been measured and show that the mobility increase rate with temperature for GC SOI transistors is similar to uniformly doped devices for temperatures down to 90 K. However, at liquid helium temperature the rate of mobility increase is larger in GC SOI than in standard devices because of the different mobility scattering mechanisms. The analog properties of GC SOI devices have been investigated down to 4.16 K and show that because of its better transconductance and output conductance, an intrinsic voltage gain improvement with temperature is also obtained for devices in the whole studied temperature range. GC devices are also capable of reducing the impact ionization due to the high electric field in the drain region, increasing the drain breakdown voltage of fully-depleted SOI MOSFETs at any studied temperature and the kink voltage at 4.16 K.
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