Artigos
URI permanente para esta coleçãohttps://repositorio.fei.edu.br/handle/FEI/798
Navegar
3 resultados
Resultados da Pesquisa
Artigo 54 Citação(ões) na Scopus Impact of the series resistance in the I-V characteristics of junctionless nanowire transistors and its dependence on the temperature(2012-01-05) Rodrigo Doria; TREVISOLI, R. D.; Michelly De Souza; Marcelo Antonio PavanelloThe effect of the source/drain parasitic resistance (R S) on the I-V characteristics of Junctionless Nanowire Transistors (JNTs) has been evaluated through experimental and simulated data. The impact of several parameters such as the temperature, the fin width, the total doping concentration, the source/drain length and the source/drain doping concentration on R S has been addressed. The source/drain parasitic resistance presented by JNTs was compared to the one presented by classical inversion mode (IM) triple gate devices, showing opposite behavior with the temperature variation in IM triple transistors and JNTs. In the latter, a reduction on R S is noted with the temperature increase, which is related to the incomplete ionization. This effect inhibits the presence of a Zero Temperature Coefficient (ZTC) operation bias in the Junctionless devices.Artigo 8 Citação(ões) na Scopus Drain current and short channel effects modeling in junctionless nanowire transistors(2013-01-05) TREVISOLI, R. D.; Rodrigo Doria; Michelly De Souza; Marcelo Antonio Pavanello© 2013, Brazilian Microelectronics Society. All rights reserved.Junctionless nanowire transistors (JNTs) are considered promising for the sub-20 nm era, since they provide a great scalability without the need for rigorously controlled doping techniques. In this work, the modeling of triple-gate JNTs is addressed, focusing on the short-channel effects. Analytical expressions for the subthreshold slope, threshold voltage roll-off and drain induced barrier lowering are presented. The model is validated using tridimensional numerical simulations.Artigo 0 Citação(ões) na Scopus The roles of the gate bias, doping concentration, temperature and geometry on the harmonic distortion of junctionless nanowire transistors operating in the linear regime(2014-05-05) Rodrigo Doria; TREVISOLI, R.; Michelly De Souza; ESTRADA, M.; CERDEIRA, A.; Marcelo Antonio Pavanello© 2014, Journal of Integrated Circuits and Systems 2014. All rights received.The linearity of Junctionless nanowire transistors operating in the linear regime has been evaluated through experimental data and numerical simulations. The influences of the fin width, the gate bias, the temperature, the doping concentration and the geometry on the overall linearity have been evaluated. The increase of the series resistance associated both to the variation of the physical parameters and the incomplete ionization effect has shown to improve the second order distortion and degrade the third order one.