Artigos
URI permanente para esta coleçãohttps://repositorio.fei.edu.br/handle/FEI/798
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6 resultados
Resultados da Pesquisa
- Applying the diamond layout style for FinFET(2012-12-02) NETO, E. D.; Salvador GimenezThe FinFET devices have been on focus in recent years due its elevated gate control capability over the channel region, what gives this technology a scalability advantage against others. The planar Diamond MOSFET layout, on the other hand, has also shown great results regarding its possible use on integrated circuits applications. In this paper, the concept of the Diamond layout style is extended to its three-dimensional version, the Diamond FinFET. 3D numerical simulations are performed in order to compare the possible advantages and disadvantages between this innovative layout style and its conventional counterpart, keeping the same gate area, geometric factor and bias conditions. It is shown that this new device inherits the qualities of its planar MOSFET version and it is proved that it can reduce significantly the die area of the analog and digital (mixed) low-power low-voltage integrated circuits due to its high capability as current driver. © The Electrochemical Society.
- Comparative experimental study between diamond and conventional MOSFET(2010-01-05) Salvador Gimenez; ALATI, D.M.The focus of this work is to perform the experimental comparative study between Diamond and the conventional MOSFET counterpart in order to verify the benefits observed by three dimensional numerical simulations, considering the same geometric factor, die area and bias conditions, as described in first publication of Diamond style layout. The devices were manufactured by using the commercial manufacture CMOS process from 0.35μm AMI (On-Semiconductor) that is available in MOSIS Educational Program (MEP). The experimental results prove that Diamond MOSFET presents a better performance than one found in equivalent conventional transistor, except in relation to the Early voltage, due the higher impact ionization in the drain region than one observed in the conventional counterpart. Therefore the Diamond layout style is an important alternative to improve the performance of the analog, current drivers and pass switches integrated circuits applications. ©The Electrochemical Society.
- X-ray radiation effects in the circular-gate transistors(2011-01-05) CIRNE, K. H.; Marcilei Aparecida Guazzelli; DE LIMA, J. A.; SEIXAS JUNIOR, L. E.; Salvador GimenezThis work performs two experimental comparative analyses of the x-ray radiation effects in the Conventional, Wave and Overlapping-Circular-Gate nMOSFETs. In the first experiment, the x-ray radiation influence is studied without biasing the devices during the irradiation process, considering two channel lengths and after they have been exposed up to a x-ray irradiation of 1.5 Grad and with a dose ratio of 22 Mrad/min. The second one performs an experimental comparative study of the x-ray radiation influence between the Conventional and Overlapping-Circular Gate nMOSFET for a channel length equal to 12 μm, when they are submitted to the x-ray irradiation of 60 Mrad and maintaining the same bias conditions (overdrive gate and drain voltages) during the irradiation process. In both studies, we observe that the Overlapping-Circular Gate layout style presents higher x-ray irradiation robustness than those found in the other transistors studied, due to the absence of the bird's beak in Overlapping-Circular Gate MOSFET. ©The Electrochemical Society.
- Experimental study of the OCTO SOI nMOSFET and its application in analog integrated circuits(2012-09-02) FINO, L. N. D. S.; RENAUX, C.; FLANDRE, D.; Salvador GimenezThis paper presents an experimental comparative study between the OCTO, Diamond and Conventional Silicon-On-Insulator nMOSFETs (OSM, DSM and CSM, respectively), considering the same bias condition for all devices. The first comparison between the OSM and the CSM counterpart considers the same gate area and the second between the OSM and DSM regards the same geometric factor, in order to verify the benefits of the octagonal gate geometry, that uses the longitudinal corner effect to increase the resultant longitudinal electric field along of the channel, to improve the device performance and consequently to enhance the performance of analog integrated circuits. These characteristics can be observed on the main analog parameters such as drain current in saturation region, maximum transconductance, transconductance by drain current, voltage gain, unity voltage gain frequency and Early voltage. © The Electrochemical Society.
- Experimental validation of the drain current analytical model of the fully depleted diamond SOI nMOSFETs by using paired t-test statistical evaluation(2012-09-02) PERUZZI, V. V.; RENAUX, C.; FLANDRE, D.; Salvador GimenezThe focus of this work is to validate the drain current analytical model of the Fully Depleted Diamond SOI nMOSFETs, by applying the paired t-test statistical evaluation with experimental data of the six different samples of integrated circuits containing different Diamond SOI MOSFETs and Conventional ones counterparts. Two parameters are considered in this work: maximum transconductance and saturation drain current. We observe that, for the most cases (worst case is around 85% of the repeatability for the saturation drain current), the Diamond drain current analytical model is capable to reproduce a similar statistical behavior than the one observed for the conventional SOI nMOSFET counterpart, considering the same bias conditions and SOI CMOS manufacturing process of the integrated circuits. © The Electrochemical Society.
- Application of junctionless nanowire transistor in the self-cascode configuration to improve the analog performance(2012-09-02) Rodrido Doria; TREVISOLI, R. D.; Michelly De Souza; Marcelo Antonio PavanelloThe self-cascode (SC) configuration consists in a series association of two transistors with tied gates usually applied to improve the analog performance of MOS devices. This paper compares the analog parameters of single Junctionless transistors with the ones presented by self-cascode associations composed by two Junctionless devices with identical or different fin widths (symmetric and asymmetric, respectively). The transconductance to the drain current ratio, the Early voltage (VEA) and the intrinsic voltage gain (AV) have been evaluated for both single devices and SC structures. It has been shown that the SC configurations, specially the asymmetric ones, present a strong reduction of the drain conductance (gD) with respect to single devices, resulting in an increase of VEA and AV, which can be higher than 30 dB depending on the bias conditions. © The Electrochemical Society.