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URI permanente para esta coleçãohttps://repositorio.fei.edu.br/handle/FEI/5120

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Implementation of high performance operational transconductance amplifiers using graded-channel SOI nMOSFETs
(2005-05-20) Salvador Gimenez; Marcelo Antonio Pavanello; Joao Antonio Martino; FLANDRE, D.
This paper presents the performance of operational transconductance amplifiers (OTAs) fabricated with Graded-Channel (GC) SOI nMOSFETs at room temperature. Different design targets were taken in account such as similar power dissipation, transconductance over drain current ratio and die area. Comparisons with high voltage gain and high unit voltage gain frequency OTAs made with conventional SOI nMOSFETs are performed showing that the GC OTAs present larger open-loop voltage gain without degrading unit voltage gain frequency, the phase margin, and slew rate with a significant required die area reduction depending on used LLD/L ratio. Experimental results and SPICE simulations are used to validate the analysis.
Analysis of deep submicrometer bulk and fully depleted SOI nmosfet analog operation at cryogenic temperatures
(2005-05-20) Marcelo Antonio Pavanello; Joao Antonio Martino; SIMOEN, E.; CLAEYS, C.
The increased demand for mixed mode digital-analog circuits is playing an important role nowadays. As the temperature of operation is decreased well-known improvements in the digital characteristics as reduction of the subthreshold slope and increased carrier mobility are obtained leading to better performance characteristics without scaling the dimensions. In this work, the impact of the temperature reduction on the analog characteristics of deep submicrometer bulk and fully depleted SOI nMOSFETs is compared. It is shown that the Early voltage does not vary appreciably with temperature and the intrinsic gain is substantially improved in bulk deep submicrometer transistors. On the other hand, deep submicrometer fully depleted SOI can operate at reduced bias current to bias the same load in base-band applications.
Low temperature and channel engineering influence on harmonic distortion of SOI nMOSFETs for analog applications
(2005-05-20) Marcelo Antonio Pavanello; CERDEIRA, A.; ALEMAN, M. A.; Joao Antonio Martino; VANCAILLE, L.; FLANDRE, D.
An evaluation of the harmonic distortion in conventional and graded-channel SOI MOSFETs is performed from room temperature down to 90 K. The total harmonic distortion as a function of the transconductance over drain current ratio has been adopted as figure of merit. It is shown that the total harmonic distortion increases as the input voltage rises and the temperature is lowered. The use of lateral channel engineering in graded-channel transistors appreciably reduces the total harmonic distortion. The dependence of harmonic distortion on length of the lightly doped region is very weak.
Analysis of silicon thickness reduction on analog parameters of GC GAA SOI transistors operating up to 300°C
(2006-09-01) SANTOS, C. D. G. DOS; Marcelo Antonio Pavanello; Joao Antonio Martino
This paper analyzes the impact of silicon film thickness reduction in some analog parameters of Gate-All-Around (GAA) transistors using the graded-channel (GC) architecture. The study was done at high temperatures (up to 300°C) through two-dimensional simulations. As the silicon film is reduced an improvement on the Early voltage was observed. However, for GC GAA devices this improvement is more pronounced at room temperature than at high temperatures. The output swing voltage (Vos) was also studied and it decreases while reducing the silicon thickness. Regarding the GC GAA the Vos is larger than conventional GAA in 50 nm thick transistors. © 2006 The Electrochemical Society.
Early voltage behavior in circular gate SOI nMOSFET using 0.13 μm partially-depleted SOI CMOS technology
(2006-09-01) Salvador Gimenez; FERREIRA, R. M. G.; Joao Antonio Martino
This paper studies the Early voltage behavior in circular gate partially-depleted SOI nMOSFET. The drain/source asymmetric effects are considered in terms of drain current as a function of the gate and drain voltages. Drain current comparisons with rectangular gate partially-depleted SOI nMOSFET are performed, regarding the same effective channel length and width. Experimental results and three-dimensional simulations are used to qualify the results. © 2006 The Electrochemical Society.
Analysis of self-heating effect in graded-channel silicon-on-insulator nMOSFETs
(2007-08-28) COSTA, S. E. DE S.; Marcelo Antonio Pavanello; Joao Antonio Martino
This paper presents a Self-Heating (SH) analysis using conventional Silicon-On-Insulator (SOI) in comparison to Graded-Channel (GC) SOI nMOSFETs devices. The analysis is performed comparing devices with the same mask channel length and with the same effective channel length. Two-dimensional numerical simulations are performed in both studies considering the lattice heating. The models and the thermal conductive constant used in these simulations are also presented. It is demonstrated that GC devices with the same mask channel length presents similar occurrence of SH independently of the length of lightly doped region despite the larger drain current. On the other hand, for similar effective channel length, the SH is less pronounced in GC transistors as the mask channel length has to be increased in order to compensate the current difference. © 2006 The Electrochemical Society.
Influence of the tunneling gate current on C-V curves
(2006-08-28) RODRIGUE, M.; SONNENBERG, V.; Joao Antonio Martino
This paper presents a study of the tunneling gate current influence on the Capacitance vs. Voltage curve in deep submicrometer CMOS technology. Two-dimensional numerical simulations are performed considering thin gate oxide and N+ polysilicon as a gate material. The influence of the tunneling gate current on the polysilicon depletion region is also analysed. It is observed that the tunneling current masks the polysilicon depletion effect due to the large increase of the substrate silicon depletion region. © 2006 The Electrochemical Society.
Influence of non-vertical sidewall on finfet threshold voltage
(2006-08-28) Renato Giacomini; Joao Antonio Martino
The FinFET structure is one of the most promising architecture approaches to double-gate devices. Due to limitations of process uniformity, most fabricated FinFETs have width variation along the vertical direction, resulting in non-vertical sidewalls. The impact of non-vertical sidewalls on the threshold voltage of FinFETs is studied in this work through three-dimensional simulation. The main purpose of this study is to verify the applicability of some analytical models developed to double-gate devices with parallel gates to FinFETs with inclined sidewalls. The behavior of the threshold voltage for different doping levels and silicon film width is discussed. The use of the existing models taking an average width of the silicon film as the device width is proposed and shows to be a good approximation. © 2006 The Electrochemical Society.
Series resistance influence on the linear kink effect in twin-gate partially depleted SOI nMOSFETs
(2007-09-01) DER AGOPIAN, P. G.; Joao Antonio Martino; SIMOEN, E.; CLAEYS, C.
This work elaborates on the influence of the series resistance on the linear kink effect (LKE) in twin-gate partially depleted (PD) Silicon-on-Insulator (SOI) nMOSFETs. The study is based on two-dimensional numerical simulations and is validated by experimental results. A relationship between the total resistance and the apparent mobility degradation factor is reported, showing that the twin-gate structure and a conventional SOI transistor with an external resistance both present a similar LKE reduction, The asymmetric behavior of the body potential with the interchange of the master and slave transistor of the twin-gate structure will be also shown. © 2006 The Electrochemical Society.

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