Engenharia Elétrica
URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/21
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10 resultados
Resultados da Pesquisa
- Influence of fin width and channel length on the performance of buffers implemented with standard and strained triple-gate nFinFETs(2009-09-03) Marcelo Antonio Pavanello; MARTINO, J. A.; SIMOEN, E.; ROOYACKERS, R.; COLLAERT, N.; CLAEYS, C.In this work the application of standard and strained triple-gate FinFETs in unity-gain source-follower configuration is compared. The analysis is performed by evaluating the buffer voltage gain with respect to the fin width and channel length as well as the total harmonic distortion. It is demonstrated that the application of strained material in narrow FinFETs, when the devices are operating in double-gate mode, can be beneficial for the performance of buffers in any channel length. On the other hand, for triple-gate FinFETs or quasi-planar ones the degradation of the output conductance overcomes the transconductance improvements from strained material and the performance of standard buffers is better than of strained ones. Narrow strained buffers also offer better harmonic distortion. © The Electrochemical Society.
- Impact of SEG on uniaxially strained MuGFET performance(2011-05-05) Paula Agopian; PACHECO, V. H.; MARTINO J. A.; SIMOEN, E.; CLAEYS, C.This work focuses on the impact of the source and drain Selective Epitaxial Growth (SEG) on the performance of uniaxially strained MuGFETs. With the channel length reduction, the normalized transconductance (gm.L/W) of unstressed MuGFETs decreases due to the series resistance and short channel effects (SCE), while the presence of uniaxial strain improves the gm. The competition between the series resistance (Rs) and the uniaxial strain results in a normalized gm maximum point for a specific channel length. Since the SEG structure influences both Rs and the strain in the channel, this work studies from room down to low temperature how these effects influence the performance of the triple-gate FETs. For lower temperatures, the strain-induced mobility enhancement increases and leads to a shift in the maximum point towards shorter channel lengths for devices without SEG. This shift is not observed for devices with SEG where the strain level is much lower. At 150 K the gm behavior of short channel strained devices with SEG is similar to the non SEG ones due to the better gm temperature enhancement for devices without SEG caused by the strain. For lower temperatures SEG structure is not useful anymore. © 2011 Elsevier Ltd. All rights reserved.
- Stress relaxation empirical model for biaxially strained triple-gate devices(2011-01-05) TREVISOLI, R. D.; MARTINO, J. A.; SIMOEN, E.; CLAEYS, C.; PAVANELLO, M. A.Multiple gate devices provides short channel effects reduction, been considered promising for sub 20 nm era. Strain engineering has also been considered as an alternative to the miniaturization due to the boost in the carrier mobility. The stress non-uniformity in Multiple gate devices cannot be easily considered in a TCAD device simulation without the coupled process simulation which is a cumbersome task. This work analyses the use of an analytical function to compute accurately the dependence of the strain on the device dimensions. The maximum transconductance gain and the threshold voltage shift are used as key parameters to compare simulated and experimental data. ©The Electrochemical Society.
- An analytical model for the non-linearity of triple gate SOI MOSFETs(2011-01-05) Rodrigo Doria; MARTINO, J. A.; SIMOEN, E.; CLAEYS, C.; Marcelo Antonio PavanelloThis work proposes a physically-based analytical model for the non-linearity of Triple-Gate MOSFETs. The model describes the second order harmonic distortion (HD2), usually the major non-linearity source, as a function of the device dimensions, the series resistance, the low field mobility and the mobility degradation factor (θ). The model was applied to transistors of different channel lengths and fin widths and allowed to conclude that θ is the parameter which most contributes for the increase of HD2. The model was validated for both unstrained and strained FinFETs. ©The Electrochemical Society.
- Impact of substrate rotation and temperature on the mobility and series resistance of triple-gate SOI nMOSFETs(2011-09-02) Michely De Souza; MARTINO, J. A.; SIMOEN, E.; CLAEYS, C.; Marcelo Antonio PavanelloIn this work a comparative experimental analysis of the electron mobility and parasitic source-drain series resistance of triple-gate n-channel MOSFETs as a function of the temperature is carried out. Devices with different fin widths fabricated on standard non-rotated and 45° rotated SOI substrates were analyzed for temperatures ranging from 250 K to 400 K. It is shown that the use of rotated substrate does not affect the subthreshold slope or the threshold voltage variation with temperature of these devices. On the other hand, the change in the conduction plane not only improves the mobility, but also promotes a rise of its variation with temperature. Although the fin width reduction may cause an increase of the series resistance, the increased mobility of rotated devices is responsible for the series resistance roll-off and this reduction becomes larger as the fin is narrowed. © The Electrochemical Society.
- Impact of proton irradiation on strained triple gate SOI p- and n-MOSFETs(2011-09-23) AGOPIAN, P. G. D.; MARTINO, J. A.; KOBAYASHI, D.; SIMOEN, E.; CLAEYS, C.In this work the proton irradiation influence on basic and analog parameters of triple-gate SOI MOSFETs is investigated. The studied devices are strained and unstrained p- and nMuGFETs. The type of stress considered in each case, was the stress that results in a better performance of p- (CESL) and n-devices (sSOI+CESL). Although the results showed the worse behavior for post-irradiated nMOS transistors, a higher immunity to the back interface influence was obtained for post-irradiated pMOS devices and consequently a better analog performance was observed. The unit gain frequency improved for p and nMOS post-irradiated devices. © 2011 IEEE.
- Uniaxial stress efficiency for different fin dimensions of triple-gate SOI nMOSFETs(2011-10-06) BÜHLER, Rudolf Theoderich; AGOPIAN, P. G. D.; Renato Giacomini; SIMOEN, E.; CLAEYS, C.; MARTINO, J. A.The stress profiles extracted showed that the variation in the silicon fin dimensions influence the stress levels and distributions along the silicon fin. From the analog performance view, these variations in the stress have influence on some electric parameters. The reduction of the total fin length showed no significant change in the parameters, although a reduction in the stress level was noticed, leading to the conclusion that the shift in the stress level is too small to cause a pronounced impact on the parameters. On the other hand, the reduction of the silicon fin height showed more interesting results. Despite that the standard device with smaller fin height presented a lower intrinsic voltage gain performance when compared to the reference device, when implementing strain it supersedes the reference device and presented an enhancement in the intrinsic voltage gain over the standard one up to 8 %, larger than the 5.1 % obtained for the reference device. © 2011 IEEE.
- Fin dimension influence on mechanical stressors in triple-gate SOI nMOSFETs(2013-05-16) BÜHLER, Rudolf Theoderich; SIMOEN, E.; AGOPIAN, P. G. D.; CLAEYS, C.; MARTINO, J. A.This work studies the SiGe SRB and tCESL strained triple-gate SOI nMOSFETs using experimental devices and also process and device numerical simulations. The transconductance and mobility are investigated and analyzed with the strain data obtained from process simulations, including the influence of the fin dimensions on the strain. The use of SiGe SRB and tCESL strain combined resulted in higher strain and higher maximum transconductance. © The Electrochemical Society.
- Analysis of carrier mobility in triple gate SOI nFinFET combining rotated substrate and strain(2016-11-02) RIBEIRO, T. A.; SIMOEN, E.; CLAEYS, C.; MARTINO, J. A.; Marcelo Antonio PavanelloThis paper studies the carrier mobility of triple gate SOI nFinFETs, fabricated on standard and rotated substrates, varying the fin width. The effective mobility results were extracted using the Split CV method, where FinFETs fabricated with rotated substrate show a higher maximum mobility than devices fabricated with a standard substrate. The effects of biaxial strain were also analyzed for the maximum mobility and it is shown that the strain increases the mobility for standard and rotated substrates. The mobility degradation was analyzed and compared for all devices. The results show that for standard devices the strain decreases the degradation of the mobility, whereas for the rotated devices strain results in an increase in this degradation for small fin width.
- Evaluation of triple-gate FinFETs with SiO2-HfO2-TiN gate stack under analog operation(2007) Marcelo Antonio Pavanello; MARTINO, J. A.; SIMOEN, E.; ROOYACKERS, R.; COLLAERT, N.; CLAEYS, C.This work presents the analog performance of nMOS triple-gate FinFETs with high-κ dielectrics, TiN gate material and undoped body from DC measurements. Different fin widths and devices with and without halo implantation are explored. No halo FinFETs can achieve extremely large gain and improved unity gain frequency at similar channel length than halo counterparts. The FinFETs with 110 nm long channel achieve an intrinsic gain of 25 dB. Extremely large Early voltages have been measured on long channel nMOS with no halo and relatively wide fins compared to the results usually reported in the literature. The large Early voltage obtained suggests that the devices operate in the onset of volume inversion due to the low doping level of the device body. © 2007 Elsevier Ltd. All rights reserved.