Engenharia Elétrica
URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/21
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6 resultados
Resultados da Pesquisa
- Harmonic distortion in symmetric and asymmetric self-cascodes of UTBB FD SOI planar MOSFETs(2019-08-05) D'OLIVEIRA, L. M.; KILCHYTSKA, V.; FLANDRE, D.; Michelly De Souza© 2019 IEEE.This paper presents an analysis of the harmonic distortion extracted from simulated results of symmetric and asymmetric self-cascode devices (S-SC and A-SC, respectively) composed by ultra-thin body and BOX fully depleted silicon-on-insulator planar MOSFETs 28 nm technological node. The results show that the A-SC effectively increases the operating drain current range for lower distortion. Comparisons with the literature show that the A-SC structures are a promising option for enhancing the circuit design flexibility for advanced MOSFETs.
- Comparative Analysis of Transcapacitances in Asymmetric Self-Cascode and Graded-Channel SOI nMOSFETs(2022-07-04) ALVES, C. R.; D'OLIVEIRA, L. M.; Michelly De Souza© 2022 IEEE.This work presents a comparative study of the transcapacitances of asymmetric self-cascode (A-SC) and graded-channel (GC) silicon-on-insulator (SOI) nMOSFETs, by means of two-dimensional numerical simulations. Simulated results show that the gate-to-drain capacitance is smaller for the ASC SOI device if compared to the GC SOI device, despite of the applied VDS.
- Asymmetric self-cascode FD SOI nMOSFETS harmonic distortion at cryogenic temperatures(2014-07-09) D'OLIVEIRA, L. M.; Rodrido Doria; Marcelo Antonio Pavanello; Michelly De Souza; KILCHYTSHA, V.; FLANDRE, D.This paper presents an analysis on the linearity of Asymmetric Self-Cascode (A-SC) of FD SOI nMOSGET transistors at cryogenic temperatures. This is achieved by evaluating experimental results of associations of transistors with various combinations of channel doping, obtained at temperatures ranging between liquid helium temperature (LHT, 4K) and room temperature (300K). It has been observed that A-SC presents better analog characteristics than the Symmetric Self-Cascode (S-SC) even at temperatures below 100K. The results show improved harmonic distortion at cryogenic temperatures and for structures composed by transistors with lower channel doping. © 2014 IEEE.
- Analysis of harmonic distortion of asymmetric self-cascode association of SOI nMOSFETs operating in saturation(2014-01-20) D'OLIVEIRA, L. M.; Rodrigo Doria; Marcelo Antonio Pavanello; Michelly De Souza; FLANDRE, D.This paper presents an experimental analysis of the harmonic distortion of asymmetric self-cascode (A-SC) association of SOI transistors. This goal is achieved by comparing the A-SC to the symmetric self-cascode (S-SC) configuration with different channel lengths. The non-linearity data have been obtained by applying the Integral Function Method to experimental measurements, for the evaluation of the total and third-order harmonic distortion. The results show that the asymmetric self-cascode provides lower total harmonic distortion than S-SC for all studied channel length associations. If a target distortion level is fixed, the A-SC enables an increase of input signal amplitude. On the other hand, smaller input signal amplitude and distortion are verified in the A-SC when fixing the output amplitude.
- Effect of high temperature on analog parameters of Asymmetric Self-Cascode SOI nMOSFETs(2014-10-29) D'OLIVEIRA, L. M.; FLANDRE, D.; Marcelo Antonio Pavanello; Michelly De SouzaThis paper presents an analysis on the high temperature operation of Silicon-on-Insulator (SOI) nMOSFETs in Asymmetric Self-Cascode (A-SC) configuration. For this analysis, experimental results in the range of 300K to 500K of A-SC structures with different channel lengths for both the drain side transistor (MD) and source side transistor (MS) are used. The effect of varying channel length under high temperatures on the A-SC association is evaluated using as figure of merit important analog parameters, such as the intrinsic voltage gain and transconductance over drain current ratio.
- Subthreshold Operation of Self-Cascode Structure Using UTBB FD SOI Planar MOSFETs(2019-10-17) D'OLIVEIRA, L. M.; KILCHYTSKA, V.; PLANES, N.; FLANDRE, D.; Michelly De Souza© 2019 IEEE.This paper presents an experimental analysis of the analog characteristics of self-cascode structures composed by 28 nm technological node ultra-thin body and BOX fully-depleted silicon-on-insulator planar MOSFETs, focusing on the subthreshold operation regime. Apart from the increased gain promoted by the reduction of front gate voltage, there is further improvement when the back-gate bias is used to reduce the threshold voltage of transistor close to the drain of the composite device, making this structure a promising option for low-power low-voltage (LPLV) analog applications.