Engenharia Elétrica
URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/21
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6 resultados
Resultados da Pesquisa
- Temperature Influence on the Electrical Properties of Vertically Stacked Nanowire MOSFETs(2021-08-27) RODRIGUES, J. C.; MARINELLO, G.; CASSE, M.; BARRAUD, S.; VINET, M.; FAYNOT, O.; Marcelo Antonio PavanelloThis paper aims at analyzing the electrical characteristics of 2-level Stacked Nanowire MOSFETs at low temperatures. Fundamental device parameters such as threshold voltage, subthreshold slope and transconductance are evaluated in the temperature range of 160K to 400K. The influence of fin width variation is also studied. An analytical model of multiple-gate nanowire MOSFETs is employed to explain the experimentally observed data. It is demonstrated that the threshold voltage increases linearly with the temperature reduction. Stacked nanowires with wider fin width presents larger threshold variation with temperature. c2021 IEEE.
- Electrical characterization of stacked SOI nanowires at low temperatures(2022-05-05) RODRIGUES, J. C.; MARINIELLO, G.; CASSE, M.; BARRAUD, S.; VINET, M.; FAYNOT, O.; Marcelo Antonio PavanelloThis work presents the electrical characterization of 2-level vertically stacked nanowire MOSFETs with variable fin widths in the temperature range from 93 K to 400 K. The basic electrical properties, such as threshold voltage, subthreshold slope, and carrier mobility are examined in the linear region with low VDS. In sequence, certain analog figures of merit such as the transconductance, the output conductance, and the voltage gain are assessed in saturation. The threshold voltage variation with temperature is linear and slightly increases for wider devices, which was satisfactorily validated by an analytical model for 3D devices. Additionally, the subthreshold slope remains close to the theoretical limit in the whole range of temperatures. The intrinsic voltage gain is weakly temperature-sensitive in the studied range regardless of the fin width. On the other hand, it increases for narrow devices in all temperatures.
- Performance of Stacked SOI Nanowires in a Wide Temperature Range(2021-09-01) RODRIGUES, J.C.; MARINIELLO, G.; CASSE, M.; BARRAUD, S.; VINET, M.; FAYNOT, O.; Marcelo Antonio PavanelloThis paper investigates the basic electrical characteristics and some analog figures of merit for 2-level vertically stacked nanowire MOSFETs with different fin widths in the temperature range of 93K up to 400 K. Basic electrical parameters such as threshold voltage, subthreshold slope and carrier mobility are evaluated in linear region. On the other hand, analog figures of merit as transconductance, output conductance and voltage gain are evaluated in saturation.
- Analog performance of n-and p-FET SOI nanowires including channel length and temperature influence(2016-01-27) PAZ, B. C.; Marcelo Antonio Pavanello; CASSE, M.; BARRAUD, S.; REIMBOLD, G.; VINET, M.; FAYNOT, O.This work aims to present the analog performance of silicon n-Type and p-MOSFET SOI nanowires. Analog parameters are shown at room temperature for both n-and p-Type, long and short channel devices with different channel width. Results for long channel n-MOS nanowires are investigated for the first time for low temperatures down to 100K. Moreover, an analysis is shown comparing the intrinsic voltage gain in nanowires and quasi-planar transistors. The mobility dependence on the temperature is found to be the key parameter to describe the behavior of both transconductance and output conductance when decreasing temperature.
- Analog performance of strained SOI nanowires down to 10K(2016-09-15) PAZ, B. C.; Marcelo Antonio Pavanello; CASSE, M.; BARRAUD, S.; REIMBOLD, G.; VINET, M.; FAYNOT, O.This work presents the analog performance of strained SOI nanowires for the first time. Triple gate MOSFETs made in strained and unstrained SOI material with variable fin widths from quasi-planar transistors to nanowires with aggressively scaled fin width are compared using experimental results in the temperature range of 300K down to 10K. Intrinsic voltage gain, transconductance and output conductance are the main figures of merit in this work. Transport characteristics are investigated showing that mobility behavior is the major responsible for the analog parameters dependence on temperature.
- Cryogenic operation of Ω-gate p-type SiGe-on-insulator nanowire MOSFETs(2018-03-19) PAZ, B. C.; Marcelo Antonio Pavanello; CASSE, M.; BARRAUD, S.; REIMBOLD, G.; VINET, M.; FAYNOT, O.This work evaluates the operation of p-type Si0.7Ge0.3-on-insulator (SGOI) nanowires from room temperature down to 5.2K. Electrical characteristics are shown for long channel devices comparing narrow Ω-gate to quasi-planar MOSFETs (wide fin width). Results show oscillations in both transconductance and gate to channel capacitance curves for temperatures smaller than 50K and fin width of 20nm due to quantum confinement effects. Improvement on the effective mobility for SGOI in comparison to SOI nanowires is still observed for devices with fin width scaled down to 20nm. Similar phonon-limited mobility contribution dependence on temperature is obtained for both narrow SGOI and SOI nanowires.