Engenharia Elétrica
URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/21
Navegar
6 resultados
Resultados da Pesquisa
- Saturation threshold voltage degradation in deep-submicrometer fully depleted SOI nMOSFETs operating in cryogenic environments(2005-10-03) Marcelo Antonio Pavanello; MARTINO, J. A.; SIMOEN, E.; CLAEYS, C.
- Analog operation of uniaxially strained FD SOI nMOSFETs in cryogenic temperatures(2007-10-04) Michelly De Souza; Marcelo Antonio Pavanello; MARTINO, J. A.; SIMOEN, E.; CLAEYS, C.
- Influence of temperature on the operation of strained triple-gate FinFETs(2008-10-09) Marcelo Antonio Pavanello; MARTINO, J. A.; SIMOEN, E.; ROOYACKERS, R.; COLLAERT, N.; CLAEYS, C.
- Effect of substrate rotation on the analog performance of triple-gate FinFETs(2009-10-08) Marcelo Antonio Pavanello; MARTINO, J. A.; SOMOEN, E.; COLLAERT, N.; CLAEYS, C.
- Uniaxial stress efficiency for different fin dimensions of triple-gate SOI nMOSFETs(2011-10-06) BÜHLER, Rudolf Theoderich; AGOPIAN, P. G. D.; Renato Giacomini; SIMOEN, E.; CLAEYS, C.; MARTINO, J. A.The stress profiles extracted showed that the variation in the silicon fin dimensions influence the stress levels and distributions along the silicon fin. From the analog performance view, these variations in the stress have influence on some electric parameters. The reduction of the total fin length showed no significant change in the parameters, although a reduction in the stress level was noticed, leading to the conclusion that the shift in the stress level is too small to cause a pronounced impact on the parameters. On the other hand, the reduction of the silicon fin height showed more interesting results. Despite that the standard device with smaller fin height presented a lower intrinsic voltage gain performance when compared to the reference device, when implementing strain it supersedes the reference device and presented an enhancement in the intrinsic voltage gain over the standard one up to 8 %, larger than the 5.1 % obtained for the reference device. © 2011 IEEE.
- Radiation hardness aspects of advanced FinFET and UTBOX devices(2012-10-04) CLAEYS, C.; AOULAICHE, M.; SIMOEN. E.; GRIFFONI, A.; KOBAYASHI, D.; MAHATME, N. N.; REED. R. A.; SCHRUMPF, R. D.; AGOPIAN, P. G. D.; MARTINO, J. A.The stringent requirements imposed by the ITRS rely on the introduction of alternative and/or new gate concepts and the implementation of advanced processing modules and materials[1]. During the last decade, alternative gate concepts, with an evolution from planar single gate to double gate, multi-gate FET (MugFET) or FinFET, and gate-all-around (GAA) or nanowire concepts have been extensively studied [2]. Although manufacturing issues have delayed their introduction in production lines, FinFET and MuGFET structures are presently being used for 22 nm technologies. The use of SOI devices leads to an improved radiation performance concerning single event upsets and latch-up [3], but can become worse for micro-dose effects and from a total ionizing dose point of view because of the radiation-induced interface states and trapped charge in the buried oxide [4]. © 2012 IEEE.