Engenharia Elétrica
URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/21
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5 resultados
Resultados da Pesquisa
- Sidewall angle influence on the FinFET analog parameters(2007-09-06) Renato Giacomini; MARTINO, J. A.; Marcelo Antonio PavanelloThe width variations along the vertical direction, due to process limitations, that appear in some fabricated FinFETs lead to non-rectangular cross-sectional shapes. One of the most frequent shapes is the trapezoidal (inclined sidewalls). These geometry variations may cause some changes in the device electrical characteristics. This work analyses the influence of the sidewall inclination angle on analog parameters, such as voltage gain, transconductance, output conductance, threshold voltage and also on the corner effects, through 3-D numeric simulation. © The Electrochemical Society.
- Physical characterization and reliability aspects of MuGFETs(2007-09-06) CLAEYS, C.; SIMOEN, E.; RAFI, J. M.; Marcelo Antonio Pavanello; MARTINO, J. A.Multi-gate devices are explicitly mentioned in the ITRS roadmap and have a good potential for scaling to the 32 nm and below technology nodes. Worldwide much attention is given to FinFET and MuGFET device architectures. This paper reviews some physical characterization and reliability aspects of such devices. Attention is given to aspects such as transient floating body effects, their performance at both high and low temperatures, gate coupling effects and their low frequency noise behavior. In addition, their potential radiation hardness in view of space applications is outlined. © The Electrochemical Society.
- Influence of the N-type FinFET width on the zero temperature coefficient(2007-09-07) BELLODI, M.; MARTINO, J. A.; CAMILO, L. M.; SIMOEN, E.; CLAEYS, C.This paper presents the influence of the Fin width dimension on the Zero Temperature Coefficient (ZTC) behavior for devices operating at high temperatures (from room temperature up to 573K). Besides this, a simple analytical model is presented in order to describe the ZTC behavior as the temperature increases. Three-dimensional simulations are carried out and compared with experimental results to support the interpretation presented along this work. © The Electrochemical Society.
- Simple analytical model to study the ZTC bias point in FinFETs(2007-05-11) BELLODI, M.; CAMILLO, L. M.; MARTINO, J. A.; SIMOEN, E.; CLAEYS, C.In this work we present a simple analytical model to study the Zero Temperature Coefficient (ZTC) bias point in FinFETs operating from room temperature up to 573 K. Three-dimensional simulations are carried out and compared with experimental results to qualify the results. © The Electrochemical Society.
- Low temperature operation of undoped body triple-gate FinFETs from an analog perspective(2007-09-06) Marcelo Antonio Pavanello; MARTINO, J. A.; SIMOEN, E.; ROOYACKERS R.; COLLAERT, N.; CLAEYS, CThis paper studies the temperature reduction influence on some analog figures of merit of n-type triple-gate FinFETs with undoped body, using DC measurements. It is demonstrated that the temperature reduction improves the transconductance over drain current ratio in any operational region. On the other hand, the output conductance is degraded when the temperature is reduced. The combination of these effects shows that the intrinsic gain of a L=90 nm FinFET is degraded by 3 dB when the temperature reduces from 300 K down to 100 K. A comparison with planar single gate fully depleted SOI reveals that the temperature degradation of the output conductance in FinFETs is less temperature-dependent. © The Electrochemical Society.