Engenharia Elétrica
URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/21
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5 resultados
Resultados da Pesquisa
- Harmonic distortion in symmetric and asymmetric self-cascodes of UTBB FD SOI planar MOSFETs(2019-08-05) D'OLIVEIRA, L. M.; KILCHYTSKA, V.; FLANDRE, D.; Michelly De Souza© 2019 IEEE.This paper presents an analysis of the harmonic distortion extracted from simulated results of symmetric and asymmetric self-cascode devices (S-SC and A-SC, respectively) composed by ultra-thin body and BOX fully depleted silicon-on-insulator planar MOSFETs 28 nm technological node. The results show that the A-SC effectively increases the operating drain current range for lower distortion. Comparisons with the literature show that the A-SC structures are a promising option for enhancing the circuit design flexibility for advanced MOSFETs.
- Use of back gate bias to enhance the analog performance of planar FD and UTBB SOI transistors-based self-cascode structures(2015-10-13) Rodrido Doria; FLANDRE, D.; TREVISOLLI, R.; Michelly De Souza; Marcelo Antonio PavanelloThis paper reports, for the first time, the use of back gate bias to improve the intrinsic voltage gain of self-cascode structures composed by planar FD and UTBB SOI MOSFETs. It is shown a voltage gain improvement larger than 10 dB when either a forward back bias is applied to the drain-side transistor or a reverse back bias is applied to the source side device.
- Design benefits of self-cascode configuration for analog applications in 28 FDSOI(2018-03-21) D'OLIVEIRA, L.; DE SOUZA, M.; KILCHYTSKA, V.;FLANDRE. D.; Michelly De Souza; KILCHYTSKA, V.; FLANDRE. D.© 2018 IEEE.This paper showcases SPICE simulated results of single transistors and self-cascode (SC) associations of UTBB transistors from 28FDSOI technology by ST-Microelectronics with a focus on analog integrated circuit design. This comparison demonstrates significant improvement of the voltage gain for the SC association without compromising the transconductance, especially when featuring asymmetric threshold voltages (Asymmetric Self-Cascode - A-SC).
- Subthreshold Operation of Self-Cascode Structure Using UTBB FD SOI Planar MOSFETs(2019-10-17) D'OLIVEIRA, L. M.; KILCHYTSKA, V.; PLANES, N.; FLANDRE, D.; Michelly De Souza© 2019 IEEE.This paper presents an experimental analysis of the analog characteristics of self-cascode structures composed by 28 nm technological node ultra-thin body and BOX fully-depleted silicon-on-insulator planar MOSFETs, focusing on the subthreshold operation regime. Apart from the increased gain promoted by the reduction of front gate voltage, there is further improvement when the back-gate bias is used to reduce the threshold voltage of transistor close to the drain of the composite device, making this structure a promising option for low-power low-voltage (LPLV) analog applications.
- Analysis of the Thermal Properties of Self-Cascode Structures Composed by UTBB Transistors(2020) COSTA, F. J.; TREVISOLI, R.; Michelly De Souza; Rodrigo Doria© 2020 IEEE.The focus of this work is to perform an analysis of the thermal properties of the Self-Cascode (SC) structure composed by advanced UTBB SOI MOSFETs under a selected set of back gate biases, through 2D numerical simulations. In this work, it could be observed that the SC structure presents a 50 % lower thermal resistance in comparison with a single device with similar channel length. The application of a back gate bias of 2 V to the drain-sided device or -2 V to the source-sided devices of the SC has shown a decrease of 10-16 % in the thermal resistance.