Engenharia Elétrica
URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/21
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7 resultados
Resultados da Pesquisa
- Impact of Temperature Effects in the Zero Temperature Coefficient of the Ellipsoidal MOSFET(2022-08-22) DE LIMA, M. P. B.; PEIXOTO, M. A. P.; CORREIA, M. M.; GALEMBECK, E. H. S.; Salvador Gimenez; CAMILO, L. M.© 2022 IEEE.The zero temperature coefficient (ZTC) is investigated by the simple model and three-dimensional numerical simulations in the Metal-Oxide-Semiconductor (MOS) Field Effect Transistor (MOSFET) with the ellipsoidal (EM) and conventional rectangular gate geometries (CM), considering the same channel widths (W), gate areas (AG) and bias condition (BC) technology. A simple model is used to study the behavior of the gate voltage at ZTC (VZTC) in the linear and the saturation region. The influence of the temperature mobility degradation on VZTC is analyzed for EM and CM devices. The VZTC changes in the temperature range investigated showed a temperature mobility degradation dependence and the both devices showed the same behavior. The analysis takes into account temperature dependence model parameters such as threshold voltage and mobility. The analytical predictions are in very close agreement with 3D simulations results in spite of the simplification used for the VZTC model as a function of temperature in the linear and the saturation region.
- New Hybrid Generation of Layout Styles to Boost the Electrical, Energy, and Frequency Response Performances of Analog MOSFETs(2022-01-05) GALEMBECK, E. H. S.; Salvador GimenezIEEEIt is known that the hexagonal (Diamond) layout style is capable of boosting the electrical performance and ionizing radiation tolerances of metal-oxide-semiconductor field-effect-transistors (MOSFETs). In order to further improve the figures of merit of these devices, it was proposed a hybrid gate geometry that is an evolution of the hexagonal layout style, entitled Half-Diamond. This innovative layout style is able to generate the same electrical effects that the Diamond is able to generate, and it is innovative because it is capable of further reducing the effective channel lengths of MOSFETs implemented with Diamond and rectangular layout styles. Thus, this work describes a comparative study by 3-D numerical simulations data and experimental data between the MOSFETs implemented with the Half-Diamond and Conventional layout styles. The main results found have indicated that the saturation drain current and transconductance of MOSFET layouted with Half-Diamond are 36% and 27% higher, respectively, than those measured in the Conventional MOSFET. Other results have shown that the innovative half-diamond layout style (HDLS) for MOSFETs is capable of reducing the dissipated electrical power in approximately 62% and, therefore, it is an alternative hardness-by-design strategy to remarkably improve complementary metal-oxide-semiconductor (CMOS) integrated circuits (ICs) energy efficiency. Besides, the electrical behaviors of longitudinal corner effect (LCE), parallel connection of MOSFETs with different channel lengths effect (PAMDLE), and deactivation of parasitic MOSFETs in the bird's beak regions effect (DEPAMBBRE) of the MOSFETs implemented with the HDLS are studied in detail to justify the results found.
- The Second Generation of the Layout Styles for MOSFETs to Further Boosting the Electrical Performance of Analog MOSFETs and CMOS ICs(2021-08-27) GALEMBECK, E.H. S.; SILVA, G. A. D.; Salvador Gimenez©2021 IEEE.This article describes, for the first time, the study of electrical behavior of the first element belonging to the family of Second Generation of layout styles for Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs), entitled Half-Diamond. It was conceived in order to further boosting the electrical performance of the analog MOSFETs in relation to the one found in Diamond MOSFETs (hexagonal gate shape). This innovative layout style has by objective further enhance the Longitudinal Corner Effect (LCE) and mainly the Parallel Connections of MOSFETs with Different Channel Lengths Effect (PAMDLE) by the means of further reducing of the effective channel lengths of Diamond MOSFETs in relation to those measured in the conventional (rectangular gate geometry) ones (RMs). The main results found by the three-dimensional numerical simulations indicates that the Half-Diamond MOSFET (HDM) is able to provide a saturation drain current 13% higher than the one observed in the RM counterpart. Furthermore, the electrical behaviors of LCE, PAMDLE and DEPAMBRE in HDM are analyzed in detail by observing the electrical behavior of the electrostatic potentials, longitudinal electric fields and drain current densities. c2021 IEEE.
- Experimental comparative study between the wave layout style and its conventional counterpart for implementation of analog integrated circuits(2012-09-02) NAVARENHO, S. R.; Salvador GimenezThis paper performs an experimental comparative study between the Wave layout style ("S" shape gate geometry) and the Conventional (rectangular gate geometry) counterpart in order to verify and quantify the benefits that Wave structure can bring to improve the performance of devices in analog circuit, specially in trasconductance the ratio of transconductance between drain current as a function of the ratio of the drain current normalized by the geometric factor and frequency response (voltage gain and unit voltage gain frequency). By working with Wave structure instead of conventional counterpart, it can improve the device performance in terms of drain current in the triode and saturation regions, consequently better results in the transconductance and unit voltage gain frequency gains. © The Electrochemical Society.
- Innovative layout styles to boost the MOSFET electrical performance(2014-01-05) Salvador GimenezThis paper describes how to potentiate the electrical performance of MOSFETs using non-conventional layout styles (rectangular gate geometry), without causing any extra burden to the current ICs manufacturing CMOS process. This layout approach is based on "drain-channel region-source interfaces engineering", which is capable to add new effects to the MOSFET structure that contributes to improve the analog and digital electrical parameters of MOSFETs. Besides that, some of these new structures can enhance the transistor robustness in harsh environment (high temperature and radiation). Furthermore, as a first insight into exploration of this layout approach was applied in Multi-Gate MOSFETs (FinFET) by three-dimensional simulations and the results are very promising. © 2014 The Electrochemical Society.
- Boosting the performance of the planar power MOSFET By using Diamond layout style(2014-09-05) DA SILVA, G. A.; Salvador Gimenez© 2014 IEEE.This manuscript introduces and experimentally investigates, for the first time, the Planar Power MOSFETs implemented with Diamond (hexagonal gate geometry) Metal-Oxide-Semiconductor Field Effect Transistor with different a angles, as a basic cell, in comparison to the homologous Multifinger PPM, regarding the same gate die area and bias conditions. Using the DPPM as output current driver (switch) in digital integrated circuits applications, we can remarkably boost the PPM electrical performance in relation to the MPPM, considering the same gate area (AG) and bias conditions (BC).
- Boosting the MOSFETs matching by using diamond layout style(2016-09-03) PERUZZI, V. V.; RENAUX, C.; FLANDRE, D.; Salvador Gimenez© 2016 IEEE.This paper performs an experimental comparative study of the Metal-Oxide-Semiconductor Silicon-On-Insulator (SOI) Field Effect Transistors (MOSFETs) matching, which are implemented with the hexagonal gate geometry (Diamond) and classical rectangular one. Some of the main analog parameters of 360 devices are investigated. The results demonstrate that the Diamond SOI MOSFETs with α angles equal to 53.1° and 90° are capable of boosting in more than 20% the devices matching in comparison to those observed in the typical rectangular SOI MOSFETs, regarding the same gate area and bias conditions. Therefore, the Diamond layout style is an alternative technique to reduce the MOSFETs' mismatching regarding the analog SOI CMOS ICs applications.