Engenharia Elétrica
URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/21
Navegar
4 resultados
Resultados da Pesquisa
- Experimental comparative analysis between junctionless and inversion mode nanowire transistors down to 10 nm-long channel lengths(2018-10-18) Rodrigo Doria; TREVISOLI, R.; Michelly De Souza; Marcelo Antonio Pavanello; VINET, M.; CASSE, M.; FAYNOT, O.This paper aims at presenting, for the first time, an experimental comparative analysis between the main electrical parameters of Junctionless (JNT) and inversion mode nanowire (IM) transistors fabricated in SOI technology down to channel length of 10 nm. The analysis has shown that JNTs present larger immunity to SCEs with respect to IM nanowires of similar dimensions. However, JNTs have shown poorer Ion than IM devices, which could be compensated through the application of multifin JNTs, at cost of increasing area consumption.
- Analog performance of self-cascode SOI nanowires nMOSFETs aiming at low-power applications(2018) ASSALTI, R.; Michelly De Souza; CASSE, M.; BARRAUD, S.; REIMBOLD, G.; VINET, M.; FAYNOT, O.© 2017 IEEE.This paper experimentally explores the analog performance of Self-Cascode structures composed by SOI Nanowire nMOSFETs operating near the subthreshold regime. The composite structure uses transistors with distinct channel widths, biased in several back-gate voltages, to promote different threshold voltages.
- New method for individual electrical characterization of stacked SOI nanowire MOSFETs(2017-10-18) PAZ, B.C.; CASSE, M.; BARRAUD, S.; REIMBOLD, G.; VINET, M.; FAYNOT, O.; Marcelo Antonio PavanelloA new systematic procedure to separate the electrical characteristics of advanced stacked nanowires (NWs) with emphasis on mobility extraction is presented. The proposed method is based on I-V measurements varying the back gate bias (VB) and consists of three basic main steps, accounting for VB influence on transport parameters. Lower mobility was obtained for the top GAA NW in comparison to bottom Q-NW. Temperature dependence of carrier mobility is also studied through the proposed method up to 150°C.
- Lateral spacers influence on the effective channel length of junctionless nanowire transistors(2017-10-16) TREVISOLI, R.; Rodrido Doria; Michelly De Souza; Marcelo Antonio PavanelloThis work presents a deep analysis on the effect of lateral spacers on the performance of the Junctionless Nanowire Transistors. An analytical model to account for the spacer influence on the device electrical behavior is proposed and validated through numerical simulation results.