Engenharia Elétrica
URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/21
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7 resultados
Resultados da Pesquisa
- Global and/or local strain influence on p- and nMuGFET analog performance(2011-01-05) AGOPIAN, P. G. D.; MARTINO, J. A.; SIMOEN, E.; CLAEYS, C.In this work, the analog performance is evaluated for tri-gate p-and nMuGFETs processed with and without the implementation of different global or local strain engineering techniques. For n-channel devices, the intrinsic voltage gain showed to be worse for strained devices when the fin is narrow. Only for wider fins the voltage gain increases with the strain efficiency due to mobility enhancement. Besides the voltage gain, the transconductance, output conductance and Early Voltage are also evaluated. In spite of the smaller impact of strain engineering, pMuGFETs show better analog behavior for all studied parameters. ©The Electrochemical Society.
- Comparison between SOI nMOSFET's under uniaxial and biaxial mechanical stress in analog applications(2011-09-02) DE SOUZA, M. A. S.; SOUZA, F. N.; Michelly De Souza; Marcelo Antonio PavanelloThis work presents a study comparing the analog performance of uniaxially and biaxially strained planar Silicon-on-Insulator nMOSFETs for a wide range of channel lengths. The study is performed via two-dimensional numerical and process simulation and supported by experimental measurements. The comparison between devices from the same technology with these two strained techniques demonstrated that higher intrinsic voltage gain is obtained for biaxial mechanical stress. However, the transconductance is higher for uniaxial mechanical stress for shorter devices (below 550 nm) leading to larger unity gain frequency. On the other hand, despite both strain techniques degrades the output conductance, this degradation with channel length shortening is less pronounced for devices under biaxial mechanical stress. © The Electrochemical Society.
- Application of junctionless nanowire transistor in the self-cascode configuration to improve the analog performance(2012-09-02) Rodrido Doria; TREVISOLI, R. D.; Michelly De Souza; Marcelo Antonio PavanelloThe self-cascode (SC) configuration consists in a series association of two transistors with tied gates usually applied to improve the analog performance of MOS devices. This paper compares the analog parameters of single Junctionless transistors with the ones presented by self-cascode associations composed by two Junctionless devices with identical or different fin widths (symmetric and asymmetric, respectively). The transconductance to the drain current ratio, the Early voltage (VEA) and the intrinsic voltage gain (AV) have been evaluated for both single devices and SC structures. It has been shown that the SC configurations, specially the asymmetric ones, present a strong reduction of the drain conductance (gD) with respect to single devices, resulting in an increase of VEA and AV, which can be higher than 30 dB depending on the bias conditions. © The Electrochemical Society.
- Influence of 45° Substrate Rotation on the Analog Performance of Biaxially Strained-Silicon SOI MuGFETs(2013-05-16) DE SOUZA, M. A. S.; Rodrido Doria; MARTINO, J. A.; SIMOEN, E.; CLAEYS, C.; Marcelo Antonio PavanelloIn this work the influence of the substrate rotation on the analog performance of strained SOI MuGFETs is presented. Measurements performed in fabricated devices show a degradation of the maximum transconductance at both linear and saturation regime. The substrate rotation has no influence on the output conductance. The intrinsic voltage gain and the unit gain frequency were extracted and presented a reduction promoted by substrate rotation, being more evident for a narrow fin. © The Electrochemical Society.
- Analog behavior of submicron graded-Channel SOI MOSFETs varying the channel length, doping concentration and temperature(2013-05-16) NEMER, J. P.; Michelly De Souza; FLANDRE, D.; Marcelo Antonio PavanelloIn this paper the analog performance of Graded-Channel (GC) SOI nMOSFETs with deep submicrometer channel length is presented. Experimental data of GC transistors fabricated in an industrial 150 nm fully-depleted SOI technology from OKI Semiconductors were used to adjust the two-dimensional numerical simulations, in order to analyze the devices analog behavior by extrapolating their physical parameters. The obtained results show that the larger intrinsic voltage gain improvement occurs when the length of the lightly doped region is approximately 100 nm regardless the total channel length, doping concentration and temperature. © The Electrochemical Society.
- Experimental comparison between pTFET and pFinFET under analog operation(2013) AGOPIAN, P. G. D.; MARTINO, J. A.; ROOYACKERS, R.; VANDOOREN, A.; SIMON, E.; CLAEYS, C.In this work, the analog performance of Tunnel FET and FinFET, which have a different principle of operation, is evaluated based on a comparison between them. This comparison is performed through the drain current behavior, the transconductance, the output conductance and the intrinsic voltage gain. Although the TFET devices present a smaller transconductance than the FinFET ones, the output behavior is strongly improved and results in a better performance of TFET devices when the focus is the intrinsic voltage gain. © The Electrochemical Society.
- The impact of a (Si)Ge heterojunction on the analog performance of vertical Tunnel FETs(2014-10-05) AGOPIAN, P. G. D.; MARTINO, J. A.; VANDOOREN, A.; ROOYACKERS, R.; SIMON, E.; THEAN, A.; CLAEYS, C.© The Electrochemical Society.This work studies the impact of the germanium content in the source on analog parameters of vertical nanowire Tunnel-FETs (NW-TFETs) operating in a temperature range from room temperature to 150°C. Although, the higher the germanium amount in the source the higher the on-state current, with respect to the analog applications the NW-TFETs performance depends mainly on the predominant conduction mechanism. At room temperature, TFETs for which BTBT is the predominant transport mechanism, present better analog performance, while at high temperature the device that is more trap-assisted-tunneling dependent presents the best performance due to its higher immunity to the drain electric field.