Engenharia Elétrica
URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/21
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12 resultados
Resultados da Pesquisa
Artigo de evento 0 Citação(ões) na Scopus Study of circular gate SOI nMOSFET devices at high temperatures(2008-05-12) ALMEIDA, L. M.; BELLODI, M.The aim of this work is to evaluate the drain leakage current behavior in a Circular Gate (CG) SOI nMOSFET fabricated in 0.13 μm SOI CMOS technology. This technology is analyzed operating since room temperature up to 300°C, where the channel length and the geometrical drain bias terminal influence are analyzed in the drain leakage current behavior, when the devices are operating at high temperatures, through 3D numerical simulations. Since the CG SOI nMOSFET is not a symmetrical structure, it is possible to have two different configurations as following: the one which structure is configured with external drain and another one, with internal drain. Analyzing the drain leakage current behavior as a function of channel length at high temperatures, it is possible to observe that for the same channel length, as the temperature increases, it becomes higher and it increases as the channel length reduces. On the other hand, when the devices are operating with external drain, the drain leakage current becomes lower as compared to the internal drain, for both devices operating at same conditions. The results show that the drain leakage current depends strongly on the channel length and its density distribution is non uniform along the silicon film thickness. Besides it, also was observed that the drain leakage current depends on drain terminal configuration. Then, in order to understand the drain configuration influence in the drain leakage current behavior at high temperatures, the electric field was analyzed into the silicon film.- Variability Modeling in Triple-Gate Junctionless Nanowire Transistors(2022-01-05) TREVISOLI, R.; Marcelo Antonio Pavanello; Rodrigo Doria; CAPOVILLA, C.E.; BARRAUD, S.; Michelly De SouzaIEEEThis work aims at proposing an analytical model for the variability of the threshold voltage and drain current in junctionless nanowire transistors. The model is continuous in all operation regions and has been validated through Monte Carlo simulations using a physically based drain current model and 3-D numerical simulations. A discussion about the influences of each variability source based on the proposed model is carried out. Finally, the modeled results are compared to the experimental data for a fully physical validation.
- Applying the diamond layout style for FinFET(2012-12-02) NETO, E. D.; Salvador GimenezThe FinFET devices have been on focus in recent years due its elevated gate control capability over the channel region, what gives this technology a scalability advantage against others. The planar Diamond MOSFET layout, on the other hand, has also shown great results regarding its possible use on integrated circuits applications. In this paper, the concept of the Diamond layout style is extended to its three-dimensional version, the Diamond FinFET. 3D numerical simulations are performed in order to compare the possible advantages and disadvantages between this innovative layout style and its conventional counterpart, keeping the same gate area, geometric factor and bias conditions. It is shown that this new device inherits the qualities of its planar MOSFET version and it is proved that it can reduce significantly the die area of the analog and digital (mixed) low-power low-voltage integrated circuits due to its high capability as current driver. © The Electrochemical Society.
- New Hybrid Generation of Layout Styles to Boost the Electrical, Energy, and Frequency Response Performances of Analog MOSFETs(2022-01-05) GALEMBECK, E. H. S.; Salvador GimenezIEEEIt is known that the hexagonal (Diamond) layout style is capable of boosting the electrical performance and ionizing radiation tolerances of metal-oxide-semiconductor field-effect-transistors (MOSFETs). In order to further improve the figures of merit of these devices, it was proposed a hybrid gate geometry that is an evolution of the hexagonal layout style, entitled Half-Diamond. This innovative layout style is able to generate the same electrical effects that the Diamond is able to generate, and it is innovative because it is capable of further reducing the effective channel lengths of MOSFETs implemented with Diamond and rectangular layout styles. Thus, this work describes a comparative study by 3-D numerical simulations data and experimental data between the MOSFETs implemented with the Half-Diamond and Conventional layout styles. The main results found have indicated that the saturation drain current and transconductance of MOSFET layouted with Half-Diamond are 36% and 27% higher, respectively, than those measured in the Conventional MOSFET. Other results have shown that the innovative half-diamond layout style (HDLS) for MOSFETs is capable of reducing the dissipated electrical power in approximately 62% and, therefore, it is an alternative hardness-by-design strategy to remarkably improve complementary metal-oxide-semiconductor (CMOS) integrated circuits (ICs) energy efficiency. Besides, the electrical behaviors of longitudinal corner effect (LCE), parallel connection of MOSFETs with different channel lengths effect (PAMDLE), and deactivation of parasitic MOSFETs in the bird's beak regions effect (DEPAMBBRE) of the MOSFETs implemented with the HDLS are studied in detail to justify the results found.
- Cross-coupling effects in common-source current mirrors composed by UTBB transistors(2022) JOSÉ DA COSTA, F.; TREVISOLI, R.; Rodrigo Doria© 2022 Elsevier LtdThis work performs an analysis of the cross-coupling effects influence on the performance of current mirrors composed by advanced UTBB SOI MOSFETs through 3D numerical simulations validated to experimental data of single devices. It is shown the presence of a capacitive coupling acting in the system, which can be demonstrated through the threshold voltage reduction at small distances between devices. Additionally, the temperature rise in the system due to the thermal coupling provokes a decrease in the input current as the devices become closer to each other. This is responsible for an increase of 3 % on ID2/ID1 ratio when the devices are biased at the same time and when the distance between them is lowered to 100 nm.
- The Second Generation of the Layout Styles for MOSFETs to Further Boosting the Electrical Performance of Analog MOSFETs and CMOS ICs(2021-08-27) GALEMBECK, E.H. S.; SILVA, G. A. D.; Salvador Gimenez©2021 IEEE.This article describes, for the first time, the study of electrical behavior of the first element belonging to the family of Second Generation of layout styles for Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs), entitled Half-Diamond. It was conceived in order to further boosting the electrical performance of the analog MOSFETs in relation to the one found in Diamond MOSFETs (hexagonal gate shape). This innovative layout style has by objective further enhance the Longitudinal Corner Effect (LCE) and mainly the Parallel Connections of MOSFETs with Different Channel Lengths Effect (PAMDLE) by the means of further reducing of the effective channel lengths of Diamond MOSFETs in relation to those measured in the conventional (rectangular gate geometry) ones (RMs). The main results found by the three-dimensional numerical simulations indicates that the Half-Diamond MOSFET (HDM) is able to provide a saturation drain current 13% higher than the one observed in the RM counterpart. Furthermore, the electrical behaviors of LCE, PAMDLE and DEPAMBRE in HDM are analyzed in detail by observing the electrical behavior of the electrostatic potentials, longitudinal electric fields and drain current densities. c2021 IEEE.
- Back bias impact on effective mobility of p-type nanowire SOI MOSFETs(2018-08-27) PAZ, B .C.; CASSE, M.; BARRAUD, S.; REIMBOLD, G.; VINET, M.; FAYNOT, O.; Marcelo Antonio PavanelloIn this work we investigated the impact of back bias on the effective mobility of p-type Ω-gate nanowire SOI MOSFETs. Evaluation is performed through both measurements and 3D numerical simulations. Electrostatic potential, electric field and holes density are studied through simulations to explain transconductance degradation with back bias increase. Holes mobility linear dependence on back bias is found to be related to the inversion channel density and its position along the silicon thickness. Besides, this work also sheds light on the dependence of the drain current in vertically stacked NW with back bias, as its behavior is determined by the bottom Ω-gate level.
- LCE and PAMDLE Effects from Diamond Layout for MOSFETs at High-Temperature Ranges(2021-08-05) GALEMBECK, E. H. S.; Salvador Gimenez© 1963-2012 IEEE.This article presents, for the first time, a study about of behavior of the intrinsic effects from diamond layout style [longitudinal corner effect (LCE) and PArallel connection of MOSFETs with Different channel Lengths Effect (PAMDLE)] for metal-oxide-semiconductor field-effect transistors (MOSFETs) influenced by wide high-temperature ranges. These effects are capable of boosting the electrical performance of analog MOSFETs in relation to that of the standard MOSFET (rectangular gate shape). First, we have developed an experimental comparative study between MOSFETs implemented with the hexagonal layout style diamond MOSFET (DM) and its rectangular MOSFET (RM) counterpart, regarding that they present the same channel width and gate area, operating in a wide high-temperature range (from 300 to 573 K). These devices were manufactured with the technology of bulk complementary MOS (CMOS) integrated circuits (ICs) of 180 nm. The experimental results have shown that DM has obtained a better electrical performance of analog MOSFETs than the one observed in RM counterpart (for example, gains of 67% for saturation drain current and 90% for the transconductance), regardless of temperatures in which they were exposed. 3-D numerical simulations were used to justify the better electrical performance of DMs due to the LCE and PAMDLE effects, in relation to one of the RM counterparts, by observing the behavior of electrostatic potentials, longitudinal electric fields, and drain current densities of the devices as the temperature increases. Besides, a study about the short-channel effect has shown that DM can suppress this effect more effectively than RM at room temperature due to a smaller reduction in effective channel length of DM.
- Thermal cross-coupling effects in side-by-side UTBB-FDSOI transistors(2021-11-05) COSTA, F. J.; TREVISOLI, R.; Rodrigo Doria© 2021 Elsevier LtdThe focus of this work is to perform a first-time analysis of the thermal cross-coupling of a device on a neighbor one in advanced UTBB transistors through 3D numerical simulations, validated with experimental data from the literature. In this work, it could be observed that the temperature rise due to a self-heated device can affect the performance of a neighbor one according to the distance between them and to the bias conditions. By varying the distance of the devices from 1 µm to 50 nm, it is shown an influence of the temperature rise due to a self-heated device in threshold voltage, subthreshold swing and in the maximum transconductance as well an increase in the thermal resistance of a neighbor device.
- Influence of interface traps density and temperature variation on the NBTI effect in p-Type junctionless nanowire transistors(2021-12-05) GRAZIANO, N.; COSTA, F. J.; TREVISOLI, R.; BARRAUD, S.; Rodrigo Doria© 2021 Elsevier LtdThis paper deals with the behavior of degradation by NBTI effect in pMOS junctionless nanowire transistors (JNTs). The analysis has been performed through measurements followed by 3D numerical simulations and has shown that the increase in the oxygen precursors density close to the interface leads to the reduction of the saturation in the NBTI effect when the devices operate in partial depletion regime. Such effect can be associated to the change in the flatband voltage to more negative values as well as the threshold voltage with the increase in the precursor density. In the sequence of the work, it was shown that, as the operation temperature rises, there is an increase in the degradation of the threshold voltage due to NBTI, which is more pronounced for larger gate voltages. It was concluded that this effect could be associated to the increase in the recombination rate with the temperature, which enables the occupation of a larger amount of traps.