Engenharia Elétrica
URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/21
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34 resultados
Resultados da Pesquisa
- Improved continuous model for short channel double-gate junctionless transistors(2014-09-05) PAZ, B. C.; AVILA, F.; CERDEIRA, A.; Marcelo Antonio Pavanello© 2014 IEEE.This work aims to present an evolution of a continuous model for short channel double-gate junctionless transistors, where the saturation velocity is included and model validation is spread to different doping concentrations, channel widths and shorter channel lengths. A long channel charge-based model for double-gate devices is used as a basis for the development of this model. To consider the short channel effects, the proposed model accounts for the influence of the drain bias in the channel potential, the reduction of the effective channel length in saturation regime and the saturation velocity effect for short channel transistors. Three dimensional numerical simulations will be used to validate the model.
- Interface traps density extraction through transient measurements in junctionless transistors(2022-08-05) TEICEIRA DA FONTE, E.; TREVISOLI, R.; BARRAUD S.; Rodrigo Doria© 2022 Elsevier LtdThis paper presents an extraction method for the interface traps density on Junctionless Transistors (JNTs) using an adapted charge pumping technique. To the best of our knowledge, this is the first work to apply this method in JNTs. Initially, it was stated through numerical simulations that a transient current, which increases with the trap density, is observed in the devices when the charge pumping method is applied. Then, a measurement setup was proposed to extract the pumping current resultant from a gate pulse and a mathematical expression was proposed to extract the density of trapped charges in the Oxide/Silicon interface (Nit). Aiming to demonstrate the method applicability for determining the JNTs interface quality, it was applied to simulations considering different trap densities as well as to experimental data of Junctionless Nanowire Transistors. It was observed that the method accuracy increases for larger trap densities and presents agreement to theoretical data for Nit > 1 × 1011 cm−2.
- Experimental Assessment of Variability in Junctionless Nanowire nMOS Transistors(2021-09-06) Michelly De Souza; BARRAUD, S.; CASSE, M.; VINET, M.; FAYNOR, O.; Marcelo Antonio PavanelloIn this work, experimental assessment of the variability of threshold voltage and drain current in junctionless nanowire n MOS transistors is presented. Die-to-die variability of threshold voltage and drain current is presented and compared to inversion mode nanowire with the same dimensions. Although the junctionless nanowires have shown larger threshold voltage matching coefficients than inversion mode devices, the variability obtained experimentally has shown to be smaller than predicted by some simulations reported in the literature. Also, it has been shown that as the channel length of junctionless nanowire transistors is reduced, the current variability becomes smaller than in inversion mode nanowires, at the same current level and dimensions.
- Charge Pumping-Based Method for Traps Density Extraction in Junctionless Transistors(2021) FONTE, E. T.; TREVISOLI, R.; Rodrido Doria© 2021 IEEE.A study of Junctionless Transistors (JNTs) is presented in this work, with emphasis on verifying the extraction of the interface traps density using the charge pumping method. To the best of our knowledge, this is the first work to use this method in JNTs. The method was applied to both simulated and experimental data and has shown satisfactory results.
- Application of junctionless nanowire transistor in the self-cascode configuration to improve the analog performance(2012-09-02) Rodrido Doria; TREVISOLI, R. D.; Michelly De Souza; Marcelo Antonio PavanelloThe self-cascode (SC) configuration consists in a series association of two transistors with tied gates usually applied to improve the analog performance of MOS devices. This paper compares the analog parameters of single Junctionless transistors with the ones presented by self-cascode associations composed by two Junctionless devices with identical or different fin widths (symmetric and asymmetric, respectively). The transconductance to the drain current ratio, the Early voltage (VEA) and the intrinsic voltage gain (AV) have been evaluated for both single devices and SC structures. It has been shown that the SC configurations, specially the asymmetric ones, present a strong reduction of the drain conductance (gD) with respect to single devices, resulting in an increase of VEA and AV, which can be higher than 30 dB depending on the bias conditions. © The Electrochemical Society.
- Analytical model for potential in double-gate juntionless transistors(2013-09-06) CERDEIRA, A.; ESTRADA, M.; TREVISOLI, R. D.; Rodrido Doria; Michelly De Souza; Marcelo Antonio PavanelloAn analytical model to calculate the potential at the surface and at the center of silicon layer for long-channel Junctionless transistors is derived and explained the basic details. The analytical model is compared with the numerical solution of the fundamental equations showing the validity of the assumptions considered. © 2013 IEEE.
- The influence of the substrate bias in Junctionless nanowire transistors(2013-09-06) TREVISOLI, R. D..; Rodrido Doria; Michelly De Souza; Marcelo Antonio PavanelloThis work aims at analyzing the influence of the substrate bias in the operation of Junctionless Nanowire Transistors. The analysis is based on simulated and experimental data. The discussion about the substrate influence on the devices operation is also accomplished by modeled results. The threshold voltage and the maximum transconductance dependence on the substrate bias are the key parameters under analysis. © 2013 IEEE.
- Analysis of charges densities in multiple-gates SOI nMOS junctionless(2013-09-06) MARINIELLO, G.; CERDEIRA, A.; ESTRADA, M.; Rodrido Doria; TREVISOLI, R. D.; Michelly De Souza; Marcelo Antonio PavanelloThis paper aims to analyze the charges density in multiple gates junctionless devices with different dimensions The analysis of the charge densities was done at the center of the silicon film, at the sidewall and at the top interfaces between the silicon and the gate oxide, for devices with different fin width, height and gate oxide tickness. Based on this analisys, the occurrence of corner effects in Junctionless devices is investigated. © 2013 IEEE.
- Analog operation of junctionless nanowire transistors down to liquid helium temperature(2014-07-09) TREVISOLI, R.; Michelly De Souza; Rodrido Doria; KILCHYTSHA, V.; FLANDRE, D.; Marcelo Antonio PavanelloThe aim of this work is to analyze the analog operation of Junctionless Nanowire Transistors at temperatures down to liquid helium temperature. The analysis is performed in terms of the transconductance, open loop voltage gain and output conductance for experimental long channel devices. It is shown that the temperature reduction can affect significantly the analog performance of the devices. © 2014 IEEE.
- Short channel continuous model for double-gate junctionless transistors(2014-01-20) PAZ, B. C.; Marcelo Antonio Pavanello; AVILA, F.; CERDEIRA, A.This work aims to present a continuous model of the drain current for short channel double-gate junctionless transistors, from a charge-based model for long channel double-gate devices. The proposed model is based on the influence of the drain bias in the channel potential and the reduction of the effective channel length in saturation regime, for short channel transistors. To model validation it will be used three dimensional numerical simulations.