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Comparison between the behavior of submicron Graded-Channel SOI nMOSFETs with fully- and partially-depleted operations in a wide temperature range
(201-10-14) Michelly De Souza; EMAM, M.; VANHOENACKER-JANVIER, D.; RASKIN, J. P.; FLANDRE, D.; Marcelo Antonio Pavanello
Implementando Algoritmos de Visão Computacional em VHDL
(2002-01-05) SOUZA, PAULO VINÍCIUS DE; Reinaldo Bianchi
Partidas de futebol entre robôs constituem uma atividade que possibilita a realização de experimentos reais para o desenvolvimento e testes de robôs, que apresentam comportamento inteligente e que cooperam entre si para a execução de uma tarefa, formando um time. Este artigo descreve o projeto e a implementação do sistema de visão computacional baseado em hardware reconfigurável tipo FPGA para ser utilizado em um time de robôs. Para tanto, são apresentadas a linguagem de definição de hardware VHDL, a descrição dos algoritmos de visão computacional adotados para tratar os problemas específicos do domínio estudado, bem como o sistema implementado. Finalmente, é realizada uma comparação da eficiência do sistema com implementações em software (linguagem C) dos mesmos algoritmos.
A Methodology to Model And Simulate An Environment For E-Learning
(2003) NEVE, Alessandro La;LA NEVE, ALESSANDRO; BROSSO, Maria Inês
Procesador Reprogramable para Compresión y Descompresión, PRCD en Tiempo Real de Imágenes de Video Digital
(2003-01-05) MELO, MARCO ANTONIO ASSIS DE; NEVE, A. L.
Wavelets application in electrostatic and their computing aspects.
(2004) Aldo Belardi; CARDOSO, José Roberto; SARTORI, Carlos Antonio França
Heuristically accelerated Q-learning: A new approach to speed up reinforcement learning
(2004-01-05) Reinaldo Bianchi; RIBEIRO, C. H. C.; COSTA, A. H. R.
This work presents a new algorithm, called Heuristically Accelerated Q-Learning (HAQL), that allows the use of heuristics to speed up the well-known Reinforcement Learning algorithm Q-learning. A heuristic function H that influences the choice of the actions characterizes the HAQL algorithm. The heuristic function is strongly associated with the policy: it indicates that an action must be taken instead of another. This work also proposes an automatic method for the extraction of the heuristic function H from the learning process, called Heuristic from Exploration. Finally, experimental results shows that even a very simple heuristic results in a significant enhancement of performance of the reinforcement learning algorithm. © Springer-Verlag 2004.
Wavelet's application in electrostatic and their computing aspects
(2004-01-05) Aldo Belardi; Cardoso J. R.; Sartori C. A. F.
This paper presents the mathematical basis, and some results, concerning the application of the Haar's Wavelets as the expansion function in the method of moments. Some computational optimization techniques are used, and their main aspects are stressed in the paper. As an example, the surface charge density on a finite and thin plane plate calculation is presented, in winch the main computational performance aspects are evaluated.
Application of Haar's wavelets in the method of moments to solve electrostatic problems
(2004-09-01) Aldo Belardi; ROBERTO CARDOSO J.; FRANCA SARTORI, C. A.
Presents the mathematical basis and some results, concerning the application of Haar's wavelets, as an expansion function, in the method of moments to solve electrostatic problems. Two applications regarding the evaluation of linear and surface charge densities were carried out: the first one on a finite straight wire, and the second one on a thin square plate. Some optimization techniques were used, whose main computational performance aspects are emphasized. Presents comparative results related to the use of Haar's wavelets and the conventional expansion functions. © 2004, Emerald Group Publishing Limited
Advantages of the graded-channel SOI FD MOSFET for application as a quasi-linear resistor
(2005) Cerdeira A.; Aleman M.A.; Pavanello M.A.; Martino J.A.; Vancaillie L.; Flandre D.
In this paper, we analyze the previously unexpected advantages of asymmetric channel engineering on the MOS resistance behavior in quasi-linear operation, such as used in integrated continuous-time tunable filters. The study of the two major figures of merit in such applications as on-resistance and nonlinear harmonic distortion, is supported by both measurements and simulations of conventional and graded-channel (GC) fully depleted silicon-on-insultor (SOI) MOSFETs. The quasi-linear current-voltage characteristics of GC transistors show a decrease of the on-resistance as the length of the low doped region in the channel is increased, as well as an improvement in the third-order harmonic distortion (HD3), when compared with conventional transistors. A method for full comparison between conventional and GC SOI MOSFETs is presented, considering HD3 evolution with on-resistance tuning under low voltage of operation. Results demonstrate the significant advantages provided by the asymmetrical long channel transistors. © 2005 IEEE.
SOI technology characterization using SOI-MOS capacitor
(2005) Sonnenberg V.; Martino J.A.
In this paper a set of simple methods is presented, to determine the main parameters of the silicon on insulator technology, using a thin film SOI-MOS capacitor. Methods to obtain the effective substrate doping concentration, substrate interface charge density and the buried oxide thickness using the two terminal SOI capacitor are presented. The front gate oxide thickness, the silicon film thickness, the silicon doping concentration and front and back interface charge density are obtained using a three terminal SOI-MOS capacitor. Bidimensional numerical simulations of SOI structure are performed for analyzing the high frequency capacitance vs. voltage curves and to test the proposed methods. These methods were applied experimentally and coherent results were found. © 2004 Elsevier Ltd. All rights reserved.
Protocols from perceptual observations
(2005) Needham C.J.; Santos P.E.; Magee D.R.; Devin V.; Hogg D.C.; Cohn A.G.
This paper presents a cognitive vision system capable of autonomously learning protocols from perceptual observations of dynamic scenes. The work is motivated by the aim of creating a synthetic agent that can observe a scene containing interactions between unknown objects and agents, and learn models of these sufficient to act in accordance with the implicit protocols present in the scene. Discrete concepts (utterances and object properties), and temporal protocols involving these concepts, are learned in an unsupervised manner from continuous sensor input alone. Crucial to this learning process are methods for spatio-temporal attention applied to the audio and visual sensor data. These identify subsets of the sensor data relating to discrete concepts. Clustering within continuous feature spaces is used to learn object property and utterance models from processed sensor data, forming a symbolic description. The progol Inductive Logic Programming system is subsequently used to learn symbolic models of the temporal protocols presented in the presence of noise and over-representation in the symbolic data input to it. The models learned are used to drive a synthetic agent that can interact with the world in a semi-natural way. The system has been evaluated in the domain of table-top game playing and has been shown to be successful at learning protocol behaviours in such real-world audio-visual environments. © 2005 Elsevier B.V. All rights reserved.
High performance analog operation of double gate transistors with the graded-channel architecture at low temperatures
(2005) Pavanello M.A.; Martino J.A.; Raskin J.-P.; Flandre D.
This work studies the use of channel engineering by means of graded-channel profile on double gate SOI MOSFETs for improving the analog performance and comparing their output characteristics with conventional double gate SOI transistors at low temperatures from room temperature down to 95 K. Two-dimensional simulations performed here provide a physical explanation for the improved analog device characteristics given by the double gate graded-channel MOSFETs, showing significantly reduced electric field and hence impact ionization rate, which is well known to plague the output characteristics of SOI MOSFETs in the low temperature range. The Early voltage degrades as the temperature decreases but this reduction reflects negligibly in the low frequency open loop gain for a temperature range of 150-300 K due to compensation provided by the transconductance over drain current ratio. The graded-channel structure can finally improve the intrinsic gain of conventional double gate transistor from 67 dB to 90 dB at 300 K. In the range of L LD/L between 0.20 and 0.35, the gain reaches 90 dB and is weakly temperature-dependent with less than 10% reduction in the range of 300 K down to 95 K. © 2005 Elsevier Ltd. All rights reserved.
Analysis of temperature-induced saturation threshold voltage degradation in deep-submicrometer ultrathin SOI MOSFETs
(2005) Pavanello M.A.; Martino J.A.; Simoen E.; Claeys C.
This paper presents a systematic study of the temperature lowering influence on the saturation threshold voltage degradation in ultrathin deep-submicrometer fully depleted silicon-on-insulator (SOI) MOSFETs. It is observed that the difference between the threshold voltage obtained with low and high drain bias, increases at lower temperatures for nMOSFETs, whereas it is weakly temperature-dependent for pMOSFETs. Experimental results and two-dimensional numerical simulations are used to support the analysis. The influence of applied back gate bias on threshold voltage variation is also studied. It is demonstrated that the higher doping level into the body region provided by the halo ion implantation associated to the floating-body increases both the multiplication factor and the parasitic bipolar gain as the temperature is lowered contributing to the threshold voltage degradation. The absence of halo implantation efficiently improves this degradation. The use of double gate structure, even with high body doping level, suppress the saturation threshold voltage degradation in cryogenic operation. © 2005 IEEE.
A charge-based continuous model for submicron graded-channel nMOSFET for analog circuit simulation
(2005) De Souza M.; Pavanello M.A.; Iniguez B.; Flandre D.
In this work a continuous analytical model for analog simulation of submicron asymmetrically doped silicon-on-insulator (SOI) nMOSFET using the graded-channel (GC) architecture, valid from weak to strong inversion regimes, is proposed. Analytical models accounting for mobility degradation due to the vertical field, channel length modulation, drain induced barrier lowering and velocity saturation effects have been included in the model formulation. Also the action of parasitic bipolar transistor intrinsic to the SOI MOSFET has been considered. The proposed model considers the highly doped part of the GC transistor acting as a 'main' transistor, whose drain voltage is modulated by the remaining part of the channel. Experimental results and two-dimensional simulated data were used to test the model, by comparing the drain current and some important characteristics for analog circuit design, such as the transconductance over the drain current ratio and output conductance, achieving a good agreement in both cases. © 2005 Elsevier Ltd. All rights reserved.
Impact of halo implantation on 0.13 μm floating body partially depleted SOI n-MOSFETs in low temperature operation
(2005) Pavanello M.A.; Martino J.A.; Simoen E.; Claeys C.
This work studies the effect of halo implantation on the electrical characteristics of deep-submicrometer partially depleted SOI nMOSFETs during low temperature and floating body operation. Parameters such as the drain induced barrier lowering (DIBL) and the device thermal resistance have been investigated. It is shown that the combination of floating body operation with halo implantation degrades the DIBL in the temperature range studied (90 K-300 K) in comparison to devices that did not received this implantation. The halo region causes a more pronounced negative output conductance than for the transistors without a halo implantation. An estimation of the temperature rise for a given dissipated power in both types of devices is made, based on the thermal resistance, which is derived from the output characteristics in function of the temperature. © 2005 Elsevier Ltd. All rights reserved.
A simple current model for edgeless SOI nMOSFET and a 3-D analysis
(2005) Giacomini R.; Martino J.A.
This work presents a new approach for the current model of thin-film, fully depleted SOI edgeless transistors, based on the asymmetric trapezoidal gate model. The most common current model for an edgeless transistor is obtained by taking the rectangular device drain current expression and substituting the device width by an "equivalent" device width, usually given by the average between source and drain width of the channel. However, this model does not take into account some effects that take place near the corners of the device and that have a significant influence on the current expression. The new model is tested using three-dimensional numerical simulation and experimental data. The proposed model is still simple and both simulation and experimental results show that it presents an improved performance. © 2005 Elsevier Ltd. All rights reserved.
Extração de parâmetros da tecnologia SOI através de capacitores
(2005-01-05) Victor Sonnenberg; NICOLETT, APARECIDO SIRLEY; MARTINO, JOÃO ANTONIO
Neste trabalho serão apresentadas as curvas características de Capacitores SOI-MOS e métodos de extração de parâmetros de processo e elétricos a partir destas curvas. Os métodos são testados e validados por simulações bidimensionais numéricas e aplicados experimentalmente, obtendo-se valores esperados para a tecnologia utilizad.
Contribution to application of wavelets in electrostatics Contribuição a aplicação das wavelets na eletrostática
(2005-01-05) Aldo Belardi; CARDOSO, J. R.; SARTORI, C. A. F.
This work presents the methodology from the determination the charge's superficial density, in two simple structure a to straight thread and in plane plates, both finite and submitted to a constant potential. That involves the method of the moments using as expansion function the wavelets instead of the pulse function, in order to reach a good precision and reducing the computational execution time. We also intends to take advantages of the wavelets application through the Cholesky decomposition, talking about formation of scattered matrixes, and the detection of nulls values.
Saturation threshold voltage degradation in deep-submicrometer fully depleted SOI nMOSFETs operating in cryogenic environments
(2005-10-03) Marcelo Antonio Pavanello; MARTINO, J. A.; SIMOEN, E.; CLAEYS, C.
ELECTRICAL ROTATING EQUIPMENT FAILURE DETECTION USING WAVELET BASED CURRENT SIGNATURE
(2006) BELARDI, A. A.; CARDOSO, José Roberto; SARTORI, Carlos Antonio França

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