Artigos
URI permanente para esta coleçãohttps://repositorio.fei.edu.br/handle/FEI/798
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Artigo 2 Citação(ões) na Scopus Performance of source follower buffers implemented with standard and strained triple-gate nFinFETs(2010-09-05) Marcelo Antonio Pavanello; MARTINO, J. A.; SIMOEN, E.; ROOYACKERS, R.; COLLAERT, N.; CLAEYS, C.In this work the application of standard and strained triple-gate FinFETs in unity-gain source-follower configuration is compared. The analysis is performed by evaluating the buffer voltage gain with respect to the fin width and channel length as well as the total harmonic distortion. It is demonstrated that the application of strained material in narrow FinFETs, when the devices are operating in double-gate mode, can be beneficial for the performance of buffers in any channel length. On the other hand, for triple-gate FinFETs or quasi-planar ones the degradation of the output conductance overcomes the transconductance improvements from strained material and the performance of standard buffers is better than of strained ones. Narrow strained buffers also offer better harmonic distortion.Artigo 0 Citação(ões) na Scopus Influence of fin shape and temperature on conventional and strained MuGFETs' analog parameters(2011-09-05) BUHLER, R. T.; Giacomini R.; MARTINO, J. A.This work evaluates two important technological variations of Triple-Gate FETs: the use of strained silicon and the occurrence of non-rectangular body cross-section. The anaysis is focused on the electrical parameters for analog applications, and covers a temperature range from 150 K to 400 K. The comparison of the intrinsic voltage gain between the different trapezoidal fin shapes showed that the fin shape can have a major role in some analog parameters than the use of the strained silicon technology, helping to improve those parameters under certain circumstances. The highest intrinsic voltage gains were obtained for strained devices with top fin width larger than bottom at low temperature. Besides the intrinsic voltage gain, were also studied: the threshold voltage, subthreshold swing, drain induced barrier lowering, channel resistance, total harmonic distortion, transconductance, transconductance to drain current ratio, output conductance, Early voltage, drain voltage saturation and unity gain frequency.- Analog parameters of strained non-rectangular triple gate FinFETs(2010-01-05) BÜHLER, Rudolf Theoderich; Renato Giacomini; MARTINO, J. A.The strained silicon technology together to the reduction of the temperature is studied in this paper on trapezoidal triple gate FinFETs, through three-dimensional numerical simulation, with particular focus on analog parameters. The comparison of the intrinsic voltage gain between the different trapezoidal fin shapes demonstrated that, although the strained silicon technology provided higher intrinsic voltage gain, the fin shape can have a major role in analog parameters, helping to improve those parameters under certain circumstances. Higher intrinsic voltage gains were obtained for strained devices with top fin width larger than bottom. ©The Electrochemical Society.
- Saturation threshold voltage degradation in deep-submicrometer fully depleted SOI nMOSFETs operating in cryogenic environments(2005-10-03) Marcelo Antonio Pavanello; MARTINO, J. A.; SIMOEN, E.; CLAEYS, C.
- Electron valence-band tunnelling excess noise in twin-gate silicon-on-insulator MOSFETs(2006-01-05) SIMOEN, E.; CLAEYS. C.; LUKYANCHIKOVA, N.; GARBER, N.; SMOLANKA, A.; DER AGOPIAN, P. G.; MARTINO, J. A.The impact of using a twin-gate (TG) configuration on the Electron Valence-Band (EVB) tunnelling-related floating-body effects has been studied in partially depleted (PD) SOI MOSFETs belonging to a 0.13 μm CMOS technology. In particular, the influence on the so-called linear kink effects (LKEs), including the second peak in the linear transconductance (gm) and the associated Lorentzian noise overshoot was investigated. It is shown that while there is a modest reduction of the second gm peak, the noise overshoot may be reduced by a factor of 2. At the same time, little asymmetry is observed when switching the role of the slave and the master transistor, in contrast to the case of the impact ionization related kink effects. Two-dimensional numerical simulations support the observations and show that both the gm, the second gm peak and the body potential are changed in the TG structure compared with a single transistor. © 2005 Elsevier Ltd. All rights reserved.
- Estimating temperature dependence of generation lifetime extracted from drain current transients(2006-05-01) MARTINO, J. A.; Milene Galeti; RAFI, J. M.; MERCHA, A.; SIMOEN, E.; CLAEYS, C.This paper presents an analysis of the temperature influence on the generation lifetime determination using drain-current transients in floating body partially depleted silicon-insulator n-type metal-oxide-semiconductor field effect transistors fabricated in a 0.13-μm SOI complementary metal-oxide semiconductor technology. The device parameters used to calculate the generation lifetime are studied as a function of the temperature from 20 to 80°C. A sensitivity analysis is done as a function of the gate oxide thickness and silicon film concentration, and the influence on the generation lifetime determination is studied. A simple model to estimate the generation lifetime is proposed. The model is experimentally applied and a good agreement is obtained. All the work is supported by two-dimensional numerical simulation. © 2006 The Electrochemical Society. All rights reserved.
- Impact of the twin-gate structure on the linear kink effect in PD SOI nMOSFETS(2006-08-05) AGOPIAN, P. G. D.; MARTINO, J. A.; SIMOEN, E.; CLAEYS, C.In this work, the influence of the twin-gate structure on the gate-induced floating body effects in thin gate oxide partially depleted (PD) silicon-on-insulator (SOI) nMOSFETs is investigated through two-dimensional numerical simulations, which are validated by experimental results. The asymmetric behavior of the body potential with the interchange of the master and slave transistor of the twin-gate structure will be shown, as well as the relation between the total resistance and the effective mobility degradation factor. It will be demonstrated that a similar reduction of the linear kink effect is obtained in a twin-gate structure and in a conventional SOI transistor with an external resistance in series. © 2006 Elsevier Ltd. All rights reserved.
- The temperature mobility degradation influence on the zero temperature coefficient of partially and fully depleted SOI MOSFETs(2006) CAMILO, L. M.; MARTINO, J. A.; SIMOEN, E.; CLAEYS, C.The zero temperature coefficient (ZTC) is investigated experimentally in partially (PD) and fully depleted (FD) SOI MOSFET fabricated in a 0.13 μm SOI CMOS technology. A simple model to study the behavior of the gate voltage at ZTC (VZTC) is proposed in the linear and the saturation region. The influence of the temperature mobility degradation on VZTC is analyzed for PD and FD devices. Experimental results show that the temperature mobility degradation is larger in FD than in PD devices, which is responsible for the VZTC decrement observed in FD instead of the increment observed in PD devices when the temperature increases. The analysis takes into account temperature dependence model parameters such as threshold voltage and mobility. The analytical predictions are in very close agreement with experimental results in spite of the simplification used for the VZTC model as a function of temperature in the linear and the saturation region. © 2006 Elsevier Ltd. All rights reserved.
- Impact of halo implantation on the lifetime assessment in partially depleted soi transistors(2006-11-03) Milene Galeti; MARTINO, J. A.; SIMOEN, E.; CLAEYS, C.This paper investigates the impact of the presence of a HALO implanted region on the lifetime analysis, based on a study of drain current switch-off transients. The latter were experimentally determined and compared with two-dimensional numerical simulations for PD SOI nMOSFET devices fabricated in a 0.13 μm CMOS technology. This study investigated for different channel lengths the drain current transient in relation with devices parameters such as the body potential, threshold voltage and the current density in the source/drain junctions. In the HALO devices the hole current density through the junctions between source/drain and body were not very significant, so that the influence of the junction is only due to the capacitive coupling between source/body and drain/body channel. For the channel length range studied (from 10 to 0.2μm), the transient time of HALO devices suffers from a 56% reduction. However, in the no HALO devices, there is beyond the capacitive coupling also a significant increase in the hole current density, causing a transient time reduction of 74%, for the same channel length range. copyright The Electrochemical Society.
- Impact of asymmetric channel configuration on the linearity of double-gate SOI MOSFETs(2006-04-26) Marcelo Antonio Pavanello; CERDEIRA, A.; MARTINO, J. A.; RASKIN, J. P.; FLANDRE, D.In this paper the linearity of asymmetric channel double-gate transistors, using the graded-channel (GC) configuration and Gate-All-Around architecture, operating as an amplifier, is studied in terms of lightly doped region length. The total harmonic distortion and third-order harmonic distortion are used as figures of merit. The results are compared with single-gate transistors with similar channel configuration. It is demonstrated that double-gate GC transistors at the same operation region and with similar channel configuration can present up to 20 dB less total harmonic distortion while presenting small third-order harmonic distortion. Considering similar bias voltage, the alternate component of the input sinusoidal signal of GC double-gate devices can be increased by about 200 mV to provide similar third-order harmonic distortion maintaining similar improvements of 20 dB on the total harmonic distortion. © 2006 IEEE.