Artigos
URI permanente para esta coleçãohttps://repositorio.fei.edu.br/handle/FEI/798
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Resultados da Pesquisa
- Performance of ultra-low-power SOI CMOS diodes operating at low temperatures(2011-01-05) Michelly De Souza; RUE, B.; FLANDRE, D.; Marcelo Antonio PavanelloIn this work the low temperature performance of ultra-low-power SOI CMOS diodes is presented. Experimental measurements performed in fabricated devices from 148K to 373K show that the temperature lowering can promote a significant leakage current reduction and increase of the forward current. Two-dimensional numerical simulations are used to extend the studied temperature range and analyze the doping concentration influence on the low temperature operation of these diodes. ©The Electrochemical Society.
- Impact of the series resistance in the I-V characteristics of nMOS junctionless nanowire transistors(2011-09-02) Rodrigo Doria; TREVISOLI, D. T.; Marcelo Antonio PavanelloThe series resistance (Rs) of Junctionless Nanowire Transistors (JNTs) with different doping concentrations was extracted from 473 K down to 100 K. The source/drain parasitic resistance presented by JNTs was compared to the one presented by classical inversion mode (IM) triple gate devices and the impact of the series resistance on the drain current of the devices was evaluated. The R S analysis was carried out through experimental results and devices tridimensional numerical simulations. According to the study, R S presents opposite behavior with the temperature variation in EVI triple transistors and JNTs. In the latter, a reduction on R S is noted with the temperature increase, whereas a resistance decrease is obtained with the temperature lowering in IM devices. The parasitic resistance in JNTs affects the drain current in such a way that there may not be a Zero Temperature Coefficient (ZTC) operation point. © The Electrochemical Society.
- Intrinsic gate capacitances of n-type junctionless nanowire transistors using a three-dimensional device simulation and experimental measurements(2012-09-02) MARINIELLO, G.; Rodrido Doria; TREVISOLI, R. D.; Michelly De Souza; Marcelo Antonio PavanelloJunctionless Nanowire transistors have been recently proposed as an alternative to overcome the short channel effect caused by the reduction of the transistors dimensions. These devices behave like a gated resistor due to the lack of the p-n junctions in the channel/ source and channel/drain regions. The influence of doping concentration, silicon width, silicon height and gate oxide thickness on the intrinsic gate capacitances are presented in this paper by using three-dimensional numerical simulations and experimental results of fabricated devices. Also the influence of the applied drain bias in the components of the intrinsic gate capacitances is addressed. © The Electrochemical Society.
- Analog behavior of submicron graded-Channel SOI MOSFETs varying the channel length, doping concentration and temperature(2013-05-16) NEMER, J. P.; Michelly De Souza; FLANDRE, D.; Marcelo Antonio PavanelloIn this paper the analog performance of Graded-Channel (GC) SOI nMOSFETs with deep submicrometer channel length is presented. Experimental data of GC transistors fabricated in an industrial 150 nm fully-depleted SOI technology from OKI Semiconductors were used to adjust the two-dimensional numerical simulations, in order to analyze the devices analog behavior by extrapolating their physical parameters. The obtained results show that the larger intrinsic voltage gain improvement occurs when the length of the lightly doped region is approximately 100 nm regardless the total channel length, doping concentration and temperature. © The Electrochemical Society.