Artigos
URI permanente para esta coleçãohttps://repositorio.fei.edu.br/handle/FEI/798
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16 resultados
Resultados da Pesquisa
- Impact of using Octogonal Layout Style in Planar Power MOSFETs(2022-08-22) DA SILVA, G. A.; Salvador Gimenez© 2022 IEEE.Previous studies have already shown that the use of alternative gate shapes for planar and tridimensional MOSFETs are capable of boosting their analog and digital electrical performances and their ionizing radiations robustness. In this scenario, this work has the objective to study the impact of the use of octagonal layout style (OCTO), as the basic cell, to the implementing of the Planar Power MOSFET (PPM). The main results of this paper show that the PPM layouted with OCTO layout styles, as the basic cells, are able to improve the drain saturation current (IDS-sat) about 668%%, in relation to that implemented with conventional rectangular layout style, considering that they present the same gate area and bias conditions. Therefore, this type of layout approach can be considered an alternative layout to improve the electrical performance of PPMs.
- Applying the diamond layout style for FinFET(2012-12-02) NETO, E. D.; Salvador GimenezThe FinFET devices have been on focus in recent years due its elevated gate control capability over the channel region, what gives this technology a scalability advantage against others. The planar Diamond MOSFET layout, on the other hand, has also shown great results regarding its possible use on integrated circuits applications. In this paper, the concept of the Diamond layout style is extended to its three-dimensional version, the Diamond FinFET. 3D numerical simulations are performed in order to compare the possible advantages and disadvantages between this innovative layout style and its conventional counterpart, keeping the same gate area, geometric factor and bias conditions. It is shown that this new device inherits the qualities of its planar MOSFET version and it is proved that it can reduce significantly the die area of the analog and digital (mixed) low-power low-voltage integrated circuits due to its high capability as current driver. © The Electrochemical Society.
- Radiation Hardness of GaN HEMTs to TID Effects: COTS for harsh environments(2019-09-20) BOAS A. C. V.; DE MELO, M. A. A.; Roberto Santos; Renato Giacomini; MEDINA, N. H.; SEIXAS, L. E.; FINCO, S.; PALOMO, F. R.; ROMERO-MAESTRO A.; Marcilei Aparecida GuazzelliThe COTS power transistors based in GaN were exposed to TID effects by 10-keV X-rays. These HEMTs were tested in the On- and Off-state bias-condition. Switching tests were performed before, during and after irradiation. The devices were characterized at temperatures ranging from -50°C to +75°C. The results indicate that the GaN-technology is a great candidate to be used in harsh environments.
- Comparative experimental study between diamond and conventional MOSFET(2010-01-05) Salvador Gimenez; ALATI, D.M.The focus of this work is to perform the experimental comparative study between Diamond and the conventional MOSFET counterpart in order to verify the benefits observed by three dimensional numerical simulations, considering the same geometric factor, die area and bias conditions, as described in first publication of Diamond style layout. The devices were manufactured by using the commercial manufacture CMOS process from 0.35μm AMI (On-Semiconductor) that is available in MOSIS Educational Program (MEP). The experimental results prove that Diamond MOSFET presents a better performance than one found in equivalent conventional transistor, except in relation to the Early voltage, due the higher impact ionization in the drain region than one observed in the conventional counterpart. Therefore the Diamond layout style is an important alternative to improve the performance of the analog, current drivers and pass switches integrated circuits applications. ©The Electrochemical Society.
- X-ray radiation effects in the circular-gate transistors(2011-01-05) CIRNE, K. H.; Marcilei Aparecida Guazzelli; DE LIMA, J. A.; SEIXAS JUNIOR, L. E.; Salvador GimenezThis work performs two experimental comparative analyses of the x-ray radiation effects in the Conventional, Wave and Overlapping-Circular-Gate nMOSFETs. In the first experiment, the x-ray radiation influence is studied without biasing the devices during the irradiation process, considering two channel lengths and after they have been exposed up to a x-ray irradiation of 1.5 Grad and with a dose ratio of 22 Mrad/min. The second one performs an experimental comparative study of the x-ray radiation influence between the Conventional and Overlapping-Circular Gate nMOSFET for a channel length equal to 12 μm, when they are submitted to the x-ray irradiation of 60 Mrad and maintaining the same bias conditions (overdrive gate and drain voltages) during the irradiation process. In both studies, we observe that the Overlapping-Circular Gate layout style presents higher x-ray irradiation robustness than those found in the other transistors studied, due to the absence of the bird's beak in Overlapping-Circular Gate MOSFET. ©The Electrochemical Society.
- Experimental study of the OCTO SOI nMOSFET and its application in analog integrated circuits(2012-09-02) FINO, L. N. D. S.; RENAUX, C.; FLANDRE, D.; Salvador GimenezThis paper presents an experimental comparative study between the OCTO, Diamond and Conventional Silicon-On-Insulator nMOSFETs (OSM, DSM and CSM, respectively), considering the same bias condition for all devices. The first comparison between the OSM and the CSM counterpart considers the same gate area and the second between the OSM and DSM regards the same geometric factor, in order to verify the benefits of the octagonal gate geometry, that uses the longitudinal corner effect to increase the resultant longitudinal electric field along of the channel, to improve the device performance and consequently to enhance the performance of analog integrated circuits. These characteristics can be observed on the main analog parameters such as drain current in saturation region, maximum transconductance, transconductance by drain current, voltage gain, unity voltage gain frequency and Early voltage. © The Electrochemical Society.
- Experimental validation of the drain current analytical model of the fully depleted diamond SOI nMOSFETs by using paired t-test statistical evaluation(2012-09-02) PERUZZI, V. V.; RENAUX, C.; FLANDRE, D.; Salvador GimenezThe focus of this work is to validate the drain current analytical model of the Fully Depleted Diamond SOI nMOSFETs, by applying the paired t-test statistical evaluation with experimental data of the six different samples of integrated circuits containing different Diamond SOI MOSFETs and Conventional ones counterparts. Two parameters are considered in this work: maximum transconductance and saturation drain current. We observe that, for the most cases (worst case is around 85% of the repeatability for the saturation drain current), the Diamond drain current analytical model is capable to reproduce a similar statistical behavior than the one observed for the conventional SOI nMOSFET counterpart, considering the same bias conditions and SOI CMOS manufacturing process of the integrated circuits. © The Electrochemical Society.
- Application of junctionless nanowire transistor in the self-cascode configuration to improve the analog performance(2012-09-02) Rodrido Doria; TREVISOLI, R. D.; Michelly De Souza; Marcelo Antonio PavanelloThe self-cascode (SC) configuration consists in a series association of two transistors with tied gates usually applied to improve the analog performance of MOS devices. This paper compares the analog parameters of single Junctionless transistors with the ones presented by self-cascode associations composed by two Junctionless devices with identical or different fin widths (symmetric and asymmetric, respectively). The transconductance to the drain current ratio, the Early voltage (VEA) and the intrinsic voltage gain (AV) have been evaluated for both single devices and SC structures. It has been shown that the SC configurations, specially the asymmetric ones, present a strong reduction of the drain conductance (gD) with respect to single devices, resulting in an increase of VEA and AV, which can be higher than 30 dB depending on the bias conditions. © The Electrochemical Society.
- Using OCTO SOI nMOSFET to handle high current for automotive modules(2012-Jan. 05) FINO, L. N. D. S; Salvador GimenezThis paper presents an experimental comparative study between the OCTOGONAL-Gate Silicon-on-Insulator (SOI) nMOSFET (OSM) and the conventional SOI nMOSFET (CSM) considering the same bias conditions and the same gate area (AG), in order to verify the influence of this new MOSFET layout style to handle high current for automotive modules. Analog integrated circuits (ICs) design tends to be considered an art due to a large number of variables and objectives to achieve the product specifications. The designer has to find the right tradeoffs to achieve the desired automotive specification such as low power, low voltage, high speed and high current driver. SOI MOSFET's technology is required to provide the growth of embedded electronics. This growth is driving demand for power-handling devices that are smaller yet still provide high current driver capabilities. To optimize the transistor's operation, attending the aggressive downscaling and automotive requirements, emerges the OCTO SOI nMOSFET as an alternative to answer the current driver and sizing question. In addition, this innovative layout style can provide low-power and more robustness against Electromagnetic Interference (EMI), Electro Static Discharge (ESD), according to Electromagnetic Compatibility (EMC). Copyright © 2012 SAE International.
- Back bias influence on analog performance of pTFET(2013-10-10) AGOPIAN, P. G. D.; NEVES, F. S.; MARTINO, J. A.; VANDOOREN, A.; ROOYACKERS, R.; SIMOEN, E.; CLAEYS, C.In this work the back bias influence on the analog performance of tunnel-FETs is evaluated experimentally for the first time. The analysis of the transconductance, output conductance and intrinsic voltage gain (Av) was performed by comparing the pTFET behavior with a well-known pFinFET that was fabricated using the same process flow. Numerical simulations were also performed in order to explain the pTFET behavior. Although the pTFET shows to be more susceptible to the back bias condition, it also shows to present always a better Av for all bias conditions. The best result in both devices was obtained when the back bias is near 0 V and the Av difference is around 30 dB in favor of pTFET. © 2013 IEEE.