Engenharia Elétrica
URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/21
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5 resultados
Resultados da Pesquisa
- Asymmetric Self-Cascode versus Graded-Channel SOI nMOSFETs for analog applications(2015-10-13) ASSALTI, R.; Marcelo Antonio Pavanello; FLANDRE, D.; Michelly De SouzaThis paper compares the performance of Asymmetric Self-Cascode and Graded-Channel SOI nMOSFETs, both proposed to improve the analog performance of fully depleted SOI nMOSFETs. The differences at device level are evaluated and the impact of their application in basic analog circuits, i.e. common-source amplifier, source-follower and common-source current mirror are explored through experimental results.
- Low-frequency noise in asymmetric self-cascode FD SOI nMOSFETs(2016-08-29) ASSALTI, R.; Rodrigo Doria; Marcelo Antonio Pavanello; Michelly De Souza; FLANDRE, D.This paper investigates the origin of low-frequency noise in Asymmetric Self-Cascode Fully Depleted SOI nMOSFETs biased in linear regime with regards to the variation of gate voltage and the channel doping concentration through experimental results.
- Improved analog performance of SOI Nanowire nMOSFETs Self-Cascode through back-biasing(2017-06-29) ASSALTI, R.; Michelly De Souza; CASSE, M.; BARRAUD, S.; REIMBOLD, G.; VINET, M.; FAYNOT, O.© 2017 IEEE.In this paper the analog performance of the Self-Cascode structure composed by SOI Nanowire nMOSFETs has been evaluated through experimental results. The influence of the channel width of the transistors near the source and the drain, and the back gate voltage variation have been evaluated.
- Channel width influence on the analog performance of the asymmetric self-cascode FD SOI nMOSFETs(2017-09-01) ASSALTI, R.; Michelly De Souza; FLANDRE, D.© 2017 IEEE.In this paper, the analog performance of the Asymmetric Self-Cascode structure of Fully Depleted SOI nMOSFETs has been evaluated with regards to the variation of channel width, through three-dimensional numerical simulations. The largest gain has been obtained using the narrowest transistor near the source and the widest transistor near the drain.
- Analog performance of self-cascode SOI nanowires nMOSFETs aiming at low-power applications(2018) ASSALTI, R.; Michelly De Souza; CASSE, M.; BARRAUD, S.; REIMBOLD, G.; VINET, M.; FAYNOT, O.© 2017 IEEE.This paper experimentally explores the analog performance of Self-Cascode structures composed by SOI Nanowire nMOSFETs operating near the subthreshold regime. The composite structure uses transistors with distinct channel widths, biased in several back-gate voltages, to promote different threshold voltages.