Repositório do Conhecimento Institucional do Centro Universitário FEI
 

Engenharia Elétrica

URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/21

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Resultados da Pesquisa

Agora exibindo 1 - 8 de 8
  • Artigo 8 Citação(ões) na Scopus
    Study of matching properties of graded-channel SOI MOSFETs
    (2008-01-05) Michelly De Souza; FLANDRE, D.; Marcelo Antonio Pavanello
    In this paper an overall analysis on the matching properties of Graded-Channel (GC) SOI MOSFETs in comparison to conventional SOI transistors is performed. Experimental results show that GC devices present poorer matching behavior in comparison to conventional SOI counterpart for equal mask channel length, whereas for same effective channel length, almost the same matching behavior. The analytical model for the drain current of GC devices is used to investigate the reasons for this matching worsening. Two-dimensional numerical simulations are used to validate the model-based analysis both in linear and saturation regions.
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    Artigo 17 Citação(ões) na Scopus
    Thin-film lateral SOI pin diodes for thermal sensing reaching the cryogenic regime
    (2010-09-01) Michelly De Souza; RUE, B.; FLANDRE, D.; Marcelo Antonio Pavanello
    This paper presents the performance of lateral SOI PIN diodes for temperature sensing in the range of 100 K to 400 K. Experimental results indicate that PIN diodes can be used to implement temperature sensors with high accuracy in cryogenic regime, provided that a suitable temperature range is chosen for calibration. Numerical simulations using Atlas two-dimensional simulator were performed in order to confirm this hypothesis and extend the analysis, verifying the accuracy of the existing model.
  • Artigo 16 Citação(ões) na Scopus
    Temperature and silicon film thickness influence on the operation of lateral SOI PIN photodiodes for detection of short wavelengths
    (2011-09-05) Michelly De Souza; BULTEEL, O.; FLANDRE, D.; Marcelo Antonio Pavanello
    This work presents an analysis of the temperature influence on the performance of a lateral thin-film SOI PIN photodiodes when illuminated by low wavelengths, in the range of blue and ultra-violet (UV). Experimental measurements performed from 100K to 400K showed that the optical responsitivity of SOI PIN photodetectors is affected by temperature change, being reduced at low and moderately high temperatures. Two-dimensional numerical simulations showed the same trends as in the experimental results, and were used both to investigate the physical phenomena responsible for the observed behavior as a function of the temperature as well as to predict the influence of silicon film thickness downscaling on the photodetector performance.
  • Artigo 1 Citação(ões) na Scopus
    Modeling of thin-film lateral SOI PIN diodes with an alternative multi-branch explicit current model
    (2012-01-05) LUGO-MUNOZ; MUCI, J.; ORTIZ-CONDE, A.; GARCIA-SANCHEZ, F. J.; Michelly De Souza; FLANDRE, D.; Marcelo Antonio Pavanello
    We propose the use of an alternative multi-exponential model to describe multiple conduction mechanisms in thin-film SOI PIN diodes with parasitic series resistance over a wide operating temperature range, from 90 to 390 K. This alternative multi-exponential model can be used for semiconductor junctions which exhibit multiple conduction mechanisms with series and shunt resistances. Using Thevenin's theorem and the Lambert W function, the terminal current is expressed explicitly as a function of the terminal voltage. Its explicit nature allows higher computational efficiency and makes this model better suited for repetitive simulation applications than conventional implicit models. Additionally, direct analytic differentiation and integration are possible. This alternative model is used to describe the I-V characteristics of real SOI PIN diodes.
  • Artigo 0 Citação(ões) na Scopus
    Boosting the MOSFETs matching by using diamond layout style
    (2017-04-05) PERUZZI, V. V.; RENAUX, C.; FLANDRE, D.; Salvador Gimenez
    © 2017, Brazilian Microelectronics Society. All rights reserved.This manuscript presents an experimental comparative study between the Metal-Oxide-Semiconductor (MOS) Silicon-On-Insulator (SOI) Field Effect Transistors, n-type, (nMOSFETs) matching, which are implemented with the hexagonal gate shape (Diamond) and standard rectangular ones. The main analog parameters and figures of merit of 360 devices are investigated. The results establish that the Diamond SOI MOSFETs with α angles equal to 90o can boost in more than in average -45.8% with a standard deviation of 20.1% the devices matching in comparison to those found with the typical rectangular SOI MOSFETs, concerning the same gate area and bias conditions. Consequently, the Diamond layout style is an alternative technique to reduce the nMOSFETs’ mismatching, considering the analog SOI Complementary MOS (CMOS) integrated circuits (ICs) applications.
  • Artigo 1 Citação(ões) na Scopus
    Origin of the low-frequency noise in the asymmetric self-cascode structure composed by fully depleted SOI nMOSFETs
    (2017-08-05) ASSALTI, R.; Rodrigo Doria; FLANDRE, D.; Michelly De Souza
    © 2017, Brazilian Microelectronics Society. All rights reserved.In this paper the origin of low-frequency noise in the Asymmetric Self-Cascode (A-SC) structure composed by Fully Depleted SOI nMOSFETs is investigated through experimental results. It is shown that the predominant noise source of the A-SC structure is linked to carrier number fluctuations, being governed by the noise generated in the transistor near the source. Larger channel doping concentrations degrade the quality of the Si-SiO2 interface and the gate oxide, which causes an increase of the normalized drain current noise spectral density, just as the reduction of the gate voltage overdrive, since there are few carriers in the channel. The A-SC structures have showed higher noise compared with single transistors. In saturation regime, the increase of the gate voltage overdrive has incremented the corner frequency, shifting the g-r noise to higher frequencies. Besides that, the normalized noise has been significantly increased when compared with the linear regime due to the rise of the drain current noise spectral density.
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    Artigo 0 Citação(ões) na Scopus
    Analysis of mismatch on the analog characteristics of GC SOI MOSFETs
    (2018-12-12) ALVES, C. R.; FLANDRE, D.; Michelly De Souza
    © 2018, Brazilian Microelectronics Society. All rights reserved.This paper presents an evaluation of mismatch impact on the analog characteristics of fully-depleted graded-channel (GC) SOI MOSFET. This study is carried out by means of electrical measurements and two-dimensional numerical simulations, comparing GC to uniformly doped transistors. Important basic parameters such as threshold voltage and sub-threshold slope were analyzed as well as analog parameters, namely transconductance, output conductance, Early voltage and intrinsic voltage gain.
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    Artigo 7 Citação(ões) na Scopus
    Performance of OCTO layout style on SOI MOSFET switches under high-temperature operation
    (2019-01-05) GALEMBECK, E. H. S.; FLANDRE, D.; RENAUX, C.; Salvador Gimenez
    © 2019, Brazilian Microelectronics Society. All rights reserved.The present paper performs an experimental comparative study of the main switching electrical parameters and figures of merit of the octagonal layout style for the planar Silicon-On-Insulator (SOI) Metal-Oxide-Semiconductor (MOS) Field Effect Transistors (MOSFET), named Octo SOI MOSFET (OSM), in comparison with the typical rectangular one, regarding a large range of temperature, varying from 300 K to 573 K. The devices were manufactured in a 2 µm fully-depleted SOI (CMOS) technology and are n-type. The results have shown that the OSM is capable of keeping active the Longitudinal Corner Effect (LCE), PArallel Connection of MOSFETs with Different Channel Lengths Effect (PAMDLE) and Deactivate the Parasitic MOSFETs of the Bird’s Beak Regions Effect (DEPAMBBRE), which are intrinsic effects of the gate octagonal structure of the MOSFET. Besides, it is able to present a higher electrical performance as compared to its rectangular SOI MOSFET (RSM) counterpart (same channel width and bias conditions). As an illustration, the OSM on-state drain current (ION) and off-state drain current (IOFF) are respectively 186% higher and 64% smaller as compared to those found in its RSM counterpart.