Engenharia Elétrica
URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/21
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13 resultados
Resultados da Pesquisa
Artigo de evento 1 Citação(ões) na Scopus Halo effects on 0.13 μm floating-body partially depleted SOI n-Mosfets in low temperature operation(2003-10-12) MARTINO, J. A.; Marcelo Antonio Pavanello; SIMOEN, E.; CLAEYS, C.This work studies the effect of halo implantation on the electrical characteristics of deep-submicrometer partially depleted SOI nMOSFETs during low temperature and floating body operation, Parameters such as the Drain Induced Barrier Lowering and the device thermal resistance have been investigated. It is shown that the combination of floating body operation with halo implantation degrades the DIBL in the temperature range studied (90 - 300 K) in comparison to devices that did not received this implantation. The halo region causes a more pronounced negative output conductance than for the transistors without a halo implantation. An estimation of the temperature rise for a given dissipated power in both types of devices is made, based on the thermal resistance, which is derived from the output characteristics in function of the temperature.Artigo de evento 1 Citação(ões) na Scopus Operation of double gate graded-channel transistors at low temperatures(2003-10-16) Marcelo Antonio Pavanello; MARTINO, J. A.; CHUNG, T. M.; KRANTI, A.; RASKIN, J. P.; FLANDRE, D.This work studies the use of graded-channel profile on double gate SOI MOSEETs from room temperature down to 95 K with the aim of studying the analog performance. Two-dimensional simulations are performed to provide a physical explanation for the improved analog device characteristics given by the double gate graded-channel MOSFETs. It is demonstrated that double gate graded-channel MOSFETs can provide extremely improved Early voltage, high transconductance and drive current in comparison to the conventional double gate fully depleted SOI MOSFETs with similar dimensions. A degradation in the Early voltage as the temperature decreases has been found but this reduction reflects negligibly in the low frequency open loop gain for a temperature range of 150 K to 300 K due compensation provided by the transconductance to drain current ratio.Artigo de evento 0 Citação(ões) na Scopus Analysis of harmonic distortion in graded-channel SOI MOSFETS at high temperatures(2004-09-11) Marcelo Antonio Pavanello; CERDEIRA, A.; MARTINO, J. A.; ALEMAN, M. A.; FLANDRE, D.An evaluation of the harmonic distortion in conventional and graded-channel SOI MOSFETs is performed from room temperature up to 423 K. The total harmonic distortion and third order harmonic distortion have been adopted as figures of merit. It is shown that the total harmonic distortion decreases as the length of the lightly doped region is increased in GC transistors, due to reduction of the effective voltage amplitude that is applied on the conventionally doped part of the channel. On the other hand, the third order harmonic distortion increases with the length of lightly doped region. The temperature increase tends to reduce the total harmonic distortion and the third order harmonic.Artigo de evento 2 Citação(ões) na Scopus A fully analytical continuous model for graded-channel SOI MOSFET for analog applications(2004-09-11) Michelly De Souza; Marcelo Antonio Pavanello; INIGUEZ, B.; FLANDRE, D.In this work an analytical model of Graded-Channel (GC) Silicon-On-Insulator (SOI) nMOSFETs is proposed for analog applications. The model is based on a series association of two conventional SOI nMOSFETs each representing one part of the GC SOI nMOSFET channel. From this assumption, we propose a current model that considers the GC SOI MOSFET as a conventional SOI transistor, represented by one part of the channel only, in which the drain voltage is modulated by the remaining part. The proposed model has been verified through the comparison between its results and experimental measurements, presenting a good agreement. Some important characteristics for analog circuits, such as transconductance and Early voltage, are compared between the model results and experimental curves.Artigo de evento 5 Citação(ões) na Scopus Improved current mirror performance using graded-channel silicon-on-insulator devices in high temperature operation(2004-09-11) FERREIRA, R. S.; Marcelo Antonio PavanelloThis work studies the output characteristics of analog current mirror using graded-channel in comparison to conventional Silicon-On-Insulator MOSFETs in high temperature operation. The output characteristics are discussed, based on simulation and experimental results. The Mirroring Precision, Output Swing and Output Resistance are extremely improved at high temperature thanks to the reduced output conductance in graded-channel transistors.Artigo de evento 1 Citação(ões) na Scopus Evaluation of the channel engineering impact on the analog performance of deep-submicrometer partially depleted SOI MOSFETS at low temperatures(2004-09-11) Marcelo Antonio Pavanello; MARTINO, J. A.; SIMOEN, E.; CLAEYS, C.The use of partially depleted deep-submicrometer SOI nMOSFETs in mixed mode applications is discussed in terms of channel engineering and temperature of operation. It is shown that the halo implantation used to obtain better digital characteristics degrades the gain and the unity gain frequency in comparison to devices that are not subjected to this implantation.Artigo de evento 1 Citação(ões) na Scopus Behavior of Graded Channel SOI Gate-All-Around nMOSFET devices at high temperatures(2004-09-11) SANTOS, C. D. G. DOS; Marcelo Antonio Pavanello; MARTINO, J. A.; FLANDRE, D.; RASKIN, J.-P.This paper presents the behavior of Graded Channel SOI Gate-All-Around (GAA) nMOSFET at high temperatures in the range of 27°C to 300°C. Threshold voltage, subthreshold slope, maximum transconductance, zero temperature coefficient and Early voltage were investigated through three-dimensional simulations and electrical characterization. It was verified that when temperature increases, threshold voltage decreases, subthreshold slope increases and did not suffer any degradation with the LLD/L ratio increase. The maximum transconductance decreases when temperature increases, and increases for larger LLD/L ratios, and Early voltage decreases almost linearly with temperature increase. The results show the excellent behavior of GC SOI GAA nMOSFET at high temperatures compared to conventional SOI GAA devices.Artigo de evento 0 Citação(ões) na Scopus Implementation of tunable resistors using graded-channel SOI MOSFETs operating in cryogenic environments(2005-09-07) Marcelo Antonio Pavanello; CERDEIRA, A.; MARTINO, J. A.; ALEMAN, M. A.; FLANDRE, D.The performance evaluation of conventional and graded-channel SOI MOSFETs operating as tunable resistors is performed from room temperature down to 90 K. The on-resistance, total harmonic distortion and third order harmonic distortion have been adopted as figures of merit. It is shown that the on-resistance reduces with the temperature lowering and is smaller in any GC SOI than in conventional SOI due to the effective channel length reduction. The total harmonic distortion is weakly temperature dependent and decreases in GC transistors, due to reduction of the effective voltage amplitude that is applied on the conventionally doped part of the channel. On the other hand, the third order harmonic distortion is strongly temperature influenced, increasing 15 dB at 90 K with respect to room temperature operation. Conventional and GC SOI have similar third order harmonic distortion in all studied temperatures.Artigo de evento 2 Citação(ões) na Scopus Comparison between bulk and floating body partially depleted SOI nMOSFETS for high frequency analog applications operating from 300 K down to 95 K(2005-09-07) Marcelo Antonio Pavanello; MARTINO, J. A.; SIMOEN, E.; CLAEYS, C.A comparison between deep-submicrometer bulk and floating-body partially depleted (PD) SOI nMOSFET operation for high frequency analog applications is performed from room temperature down to 95 K. The transistor intrinsic gain, cutoff frequency and bias current are used as figures of merit for this comparison. It is demonstrated that bulk transistors can have larger intrinsic gain at any temperature of operation due to their larger Early voltage. On the other hand, the cutoff frequency is improved in PD SOI without halo due to the larger carrier mobility and velocity saturation. Also PD SOI without halo reaches a frequency of 13 GHz at 95 K, whereas bulk and PD SOI with halo reach 11 GHz for the same load capacitance of 100 fF.Artigo de evento 0 Citação(ões) na Scopus A charge-based continuous model for small-geometry graded-channel SOI MOSFET's(2005-09-07) Michelly De Souza; Marcelo Antonio PavanelloIn this work a continuous model for analog simulation of short-channel Graded-Channel (GC) Silicon-On-Insulator (SOI) nMOSFET is presented. Effects of channel length modulation and velocity saturation have been included in the model formulation, which is based on the series combination of two conventional SOI nMOSFETs, each one representing one of the regions of GC SOI MOSFET channel and its characteristics. Experimental results and numerical bidimensional simulations are used to validate the model with excellent agreement in both cases.