Engenharia Elétrica
URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/21
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11 resultados
Resultados da Pesquisa
- Saturation threshold voltage degradation in deep-submicrometer fully depleted SOI nMOSFETs operating in cryogenic environments(2005-10-03) Marcelo Antonio Pavanello; MARTINO, J. A.; SIMOEN, E.; CLAEYS, C.
- Analog operation of uniaxially strained FD SOI nMOSFETs in cryogenic temperatures(2007-10-04) Michelly De Souza; Marcelo Antonio Pavanello; MARTINO, J. A.; SIMOEN, E.; CLAEYS, C.
- Influence of temperature on the operation of strained triple-gate FinFETs(2008-10-09) Marcelo Antonio Pavanello; MARTINO, J. A.; SIMOEN, E.; ROOYACKERS, R.; COLLAERT, N.; CLAEYS, C.
- Thermal sensing performance of lateral SOI PIN diodes in the 90 - 400 K range(2009-10-08) Michelly De Souza; RUE, B.; FLANDRE, D.; Marcelo Antonio Pavanello
- Effect of substrate rotation on the analog performance of triple-gate FinFETs(2009-10-08) Marcelo Antonio Pavanello; MARTINO, J. A.; SOMOEN, E.; COLLAERT, N.; CLAEYS, C.
- Electrical characterization of SOI solar cells in a wide temperature range(2010-10-14) Michelly De Souza; BULTEEL, O.; FLANDRE, D.; Marcelo Antonio Pavanello
- Analog operation of junctionless transistors at cryogenic temperatures(2010-10-14) Rodrigo Doria; Marcelo Antonio Pavanello; TREVISOLI, R. D.; Michelly De Souza; LEE, C. W.; FERAIN, I.; DEHDASHTI AKHAVAN, N.; YAN, R.; RAZAVI, P.; YU, R.; KRANTI, A.; COLINGE, J. P.
- Asymmetric self-cascode configuration to improve the analog performance of SOI nMOS transistors(2011-10-11) Michelly De Souza; FLANDRE, D.; Marcelo Antonio PavanelloIn this work an asymmetric self-cascode (SC) structure implemented in a 150nm technology have been studied as a function of the threshold voltage and length of both transistors in the structure, aiming to improve the analog characteristics of FD SOI transistors. Experimal results indicate that this structure provided improvement in comparison to single and symmetric (SC) transistors, and that it depends on the saturation voltage of both transistors. The effect of threshold voltage and length variation of both transistors have been analyzed through 2D numerical simulations. The obtained results showed that the analog characteristics of the A-SC is improved both by reducing V T,2 and increasing L 1 and/or L 2, although there would be a maximum M 2 length in which no significant g D reduction is observed. By properly choosing these parameters, a g D reduction of more than one order of magnitude can be achieved. The A-SC has shown to provide an intrinsic voltage gain improvement of more than 20dB in comparison to single devices with similar effective channel length. © 2011 IEEE.
- Analysis of the low-frequency noise of junctionless nanowire transistors operating in saturation(2011-10-06) Rodrigo Doria; TREVISOLI, R. D.; Michelly De Souza; COLINGE, J.P.; Marcelo Antonio PavanelloThis work presented the LF noise behavior of nMOS JNTs investigated by experimental results. It was shown that JNTs can present either 1/f or 1/f 2 noises, depending on their operation region and the frequency. 1/f noise has been associated to carrier number fluctuations whereas 1/f 2 can be related to defects in the depletion layer. The W mask reduction degrades S Id at higher V GT (∼ 1 V) and present negligible influence on S Id at lower V GT (∼ 0.2 V). © 2011 IEEE.
- Low-Frequency Noise of nMOS and pMOS short channel junctionless nanowire transistors(2012-10-04) Rodrido Doria; TREVISOLI, R. D.; Michelly De Souza; FERAIN, I.; DAS, S.; Marcelo Antonio PavanelloMulti-gate architecture has been considered as one of the most viable alternatives to MOS devices scaling below 22 nm nodes [1] due to its stronger robustness to the short channel effects with respect to planar architectures. In short channel devices, the control of the gate over the channel charges dramatically decreases making the use of planar devices extremely challenging. Despite providing an improved coupling between gates and channel, conventional inversion mode (IM) multi-gate structures such as Trigate and FinFETs present p-n junctions between source/drain and channel, which can become an important bottleneck for ultimate technologies in which the formation of ultra-sharp junctions is needed in order to avoid the source/drain dopants diffusion into the channel. A novel multi-gate architecture so-called Junctionless Nanowire Transistor (JNT) was recently developed to overcome this bottleneck [2-3]. The JNT consists of a silicon nanowire surrounded by gate stack and is different from multi-gate IM devices due to its doping profile which is heavy and constant between source, channel and drain without any dopant gradients. The longitudinal sections of both a pMOS and an nMOS JNT are shown in Fig. 1 where the p-type is doped with boron and the n-type ones with phosphorous. The silicon nanowire needs to have a square-section small enough to be fully depleted at low gate voltages, turning off the device. Above threshold, the current flows mainly due to bulk conduction [4]. Several papers have shown the potentiality of the JNT for technological nodes beyond 10 nm [2-6] since it provides better DIBL, subthreshold slope and analog properties than IM multi-gate transistors of similar dimensions [5,6]. Although the Low-Frequency Noise (LFN) of JNTs has been treated in different papers [7,8], only long devices have been evaluated up to now and in none of them the LFN of pMOS was addressed as proposed in the current paper. © 2012 IEEE.