Engenharia Elétrica
URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/21
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22 resultados
Resultados da Pesquisa
- Extraction of the Back Channel Mobility in SOI Nanowire MOS Transistors under Substrate Biasing(2022-07-04) BERGAMASHI, F. E.; WIRTH, G. I.; BARRAUD, S.; CASSE, M.; VINET, M.; FAYNOT, O.; Marcelo Antonio Pavanello© 2022 IEEE.In this work, an analysis of the effective mobility of SOI nanowire MOS transistors is performed by separating the mobility of electrons in the back channel, which is created when substrate bias is applied. Measurements are done in n-type devices with an Ω-gate structure and variable channel length. Both longer and shorter channel devices present higher mobility in the back channel, but strong mobility reduction is observed with the increase of the substrate bias, reaching values close to that of the front channel at strong back bias levels. This effect is independent of the applied gate voltage overdrive. Three-dimensional TCAD simulation validates the method used to separate the back channel mobility, showing that the front channel mobility is not changed by the increase in substrate bias.
- Experimental Assessment of Variability in Junctionless Nanowire nMOS Transistors(2021-09-06) Michelly De Souza; BARRAUD, S.; CASSE, M.; VINET, M.; FAYNOR, O.; Marcelo Antonio PavanelloIn this work, experimental assessment of the variability of threshold voltage and drain current in junctionless nanowire n MOS transistors is presented. Die-to-die variability of threshold voltage and drain current is presented and compared to inversion mode nanowire with the same dimensions. Although the junctionless nanowires have shown larger threshold voltage matching coefficients than inversion mode devices, the variability obtained experimentally has shown to be smaller than predicted by some simulations reported in the literature. Also, it has been shown that as the channel length of junctionless nanowire transistors is reduced, the current variability becomes smaller than in inversion mode nanowires, at the same current level and dimensions.
- Influence of fin width and channel length on the performance of buffers implemented with standard and strained triple-gate nFinFETs(2009-09-03) Marcelo Antonio Pavanello; MARTINO, J. A.; SIMOEN, E.; ROOYACKERS, R.; COLLAERT, N.; CLAEYS, C.In this work the application of standard and strained triple-gate FinFETs in unity-gain source-follower configuration is compared. The analysis is performed by evaluating the buffer voltage gain with respect to the fin width and channel length as well as the total harmonic distortion. It is demonstrated that the application of strained material in narrow FinFETs, when the devices are operating in double-gate mode, can be beneficial for the performance of buffers in any channel length. On the other hand, for triple-gate FinFETs or quasi-planar ones the degradation of the output conductance overcomes the transconductance improvements from strained material and the performance of standard buffers is better than of strained ones. Narrow strained buffers also offer better harmonic distortion. © The Electrochemical Society.
- 3D simulation of Triple-Gate MOSFETs(2010-05-19) CONDE, J.; CERDEIRA, A.; Marcelo Antonio Pavanello; KILCHYTSKA, V.; FLANDRE, D.In this paper we present a new approach of analyzing 3D structure for Triple-Gate MOSFETs with three different mesh regions, one at the top and two in the sidewalls of the fin, which allows the consideration of different carrier mobility at each region due to the crystalline orientation and technological processing. A procedure for the extraction of the mobility parameters in each region is developed. Validation of the proposed structure was made for a FinFET arrays with fixed channel length and different fin widths, obtaining a very good coincidence between experimental and simulated characteristics. © 2010 IEEE.
- Three-dimensional simulation of biaxially strained triple-gate FinFETs: A method to compute the fin width and channel length dependences on device electrical characteristics(2010-01-05) Rodrigo Doria; Marcelo Antonio PavanelloStrained devices have been the focus of recent research works due to the boost in the carrier mobility providing a drain current enhancement. Consequently, simulating strained transistors become of major importance in order to predict their characteristics. However, the non-uniformity of the stress distribution creates a dependence of the strain on the device dimensions. This dependence cannot be easily considered in a TCAD simulation. This work shows that the definition of an analytical function for the strain components can overcome this drawback in the stress simulation. Maximum transconductance gain was used as the key parameter to compare simulated and experimental data. The results obtained show mat the simulations with the analytical function agree wim the measurements. ©The Electrochemical Society.
- An analytical model for the non-linearity of triple gate SOI MOSFETs(2011-01-05) Rodrigo Doria; MARTINO, J. A.; SIMOEN, E.; CLAEYS, C.; Marcelo Antonio PavanelloThis work proposes a physically-based analytical model for the non-linearity of Triple-Gate MOSFETs. The model describes the second order harmonic distortion (HD2), usually the major non-linearity source, as a function of the device dimensions, the series resistance, the low field mobility and the mobility degradation factor (θ). The model was applied to transistors of different channel lengths and fin widths and allowed to conclude that θ is the parameter which most contributes for the increase of HD2. The model was validated for both unstrained and strained FinFETs. ©The Electrochemical Society.
- Comparison between SOI nMOSFET's under uniaxial and biaxial mechanical stress in analog applications(2011-09-02) DE SOUZA, M. A. S.; SOUZA, F. N.; Michelly De Souza; Marcelo Antonio PavanelloThis work presents a study comparing the analog performance of uniaxially and biaxially strained planar Silicon-on-Insulator nMOSFETs for a wide range of channel lengths. The study is performed via two-dimensional numerical and process simulation and supported by experimental measurements. The comparison between devices from the same technology with these two strained techniques demonstrated that higher intrinsic voltage gain is obtained for biaxial mechanical stress. However, the transconductance is higher for uniaxial mechanical stress for shorter devices (below 550 nm) leading to larger unity gain frequency. On the other hand, despite both strain techniques degrades the output conductance, this degradation with channel length shortening is less pronounced for devices under biaxial mechanical stress. © The Electrochemical Society.
- Comparative study of biaxial and uniaxial mechanical stress influence on the low frequency noise of fully depleted SOI nMOSFETs operating in triode and saturation regime(2012-09-02) DE SOUZA, M. A. S.; Rodrido Doria; Michelly De Souza; MARTINO, J. A.; Marcelo Antonio PavanelloThis paper presents an experimental comparative study of uniaxial and biaxial strain techniques influence on the low frequency noise of planar fully depleted SOI nMOSFETs operating in linear and saturation regimes. The comparison between devices from the same technology with these two strained techniques demonstrated a reduction of low frequency noise for devices with both strain technologies in linear regime for shorter devices (below 410 nm). In saturation regime the reduction of low frequency noise for uniaxial and biaxial strain also occurs, but does not depend on the channel length, and the reduction of low frequency noise in favor of both strain technologies is more pronounced for channel length of 160 nm. © The Electrochemical Society.
- Uniaxial mechanical stress influence on the low frequency noise in FD SOI nMOSFETs operating in saturation(2012-03-17) DE SAOUZA, M. A. S.; CLAEYS, C.; Rodrido Doria; Marcelo Antonio Pavanello; SIMOEN, E.This work presents a study of the influence of mechanical stress on the low frequency noise in planar SOI transistors operating in saturation. Several channel lengths were measured, and the results show a reduction of the low frequency noise for strained devices independent of the channel length, and this reduction is more effective for smaller channel lengths. © 2012 IEEE.
- Analog performance of submicron GC SOI MOSFETs(2012-03-17) NEMER J. P.; Michelly De Souza; Marcelo Antonio Pavanello; FLANDRE, D.This paper aims to demonstrate the performance of GC SOI MOSFET devices in comparison to standard SOI MOS transistors, comparing the improvements achieved by the adoption of the GC architecture in a submicron fully depleted SOI technology varying the channel length. The results obtained by two-dimensional numerical simulations show that the best improvement is obtained when the length of lightly doped region length is approximately 100 nm, independently of the total channel length. © 2012 IEEE.
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