Engenharia Elétrica
URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/21
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5 resultados
Resultados da Pesquisa
- Use of back gate bias to enhance the analog performance of planar FD and UTBB SOI transistors-based self-cascode structures(2015-10-13) Rodrido Doria; FLANDRE, D.; TREVISOLLI, R.; Michelly De Souza; Marcelo Antonio PavanelloThis paper reports, for the first time, the use of back gate bias to improve the intrinsic voltage gain of self-cascode structures composed by planar FD and UTBB SOI MOSFETs. It is shown a voltage gain improvement larger than 10 dB when either a forward back bias is applied to the drain-side transistor or a reverse back bias is applied to the source side device.
- Analog performance improvement of self-cascode structures composed by UTBB transistors using back gate bias(2015-11-20) Rodrido Doria; TREVISOLI, R.; Michelly De Souza; Marcelo Antonio Pavanello; FLANDRE, D.This paper explores the use of the back gate bias to enhance the analog performance of self-cascode structures composed by 25nm-long UTBB SOI MOSFETs. It is shown, for the first time, that the use of back gate bias can improve the intrinsic voltage gain by 15 dB, making it larger than the one presented by a 50nm-long single device.
- Use of back gate bias to improve the performance of n- and p-type UTBB transistors-based self-cascode structures applied to current mirrors(2017-10-10) Rodrido Doria; TREVISOLI, R.; Michelly De Souza; Marcelo Antonio Pavanello; FLANDRE, D.This paper aims at demonstrating, for the first time, the use of back bias to improve the analog performance of current mirrors composed by self-cascode structures with 25 nm-long n- and p-type UTBB SOI MOSFETs. The use of back gate bias has shown to enhance the intrinsic gain of p-type devices by about 7 dB, making it higher than the one from a single device with equivalent channel length whereas the mirroring precision has shown to be improved by 20 % with respect to single devices.
- Subthreshold Operation of Self-Cascode Structure Using UTBB FD SOI Planar MOSFETs(2019-10-17) D'OLIVEIRA, L. M.; KILCHYTSKA, V.; PLANES, N.; FLANDRE, D.; Michelly De Souza© 2019 IEEE.This paper presents an experimental analysis of the analog characteristics of self-cascode structures composed by 28 nm technological node ultra-thin body and BOX fully-depleted silicon-on-insulator planar MOSFETs, focusing on the subthreshold operation regime. Apart from the increased gain promoted by the reduction of front gate voltage, there is further improvement when the back-gate bias is used to reduce the threshold voltage of transistor close to the drain of the composite device, making this structure a promising option for low-power low-voltage (LPLV) analog applications.
- Analysis of the Thermal Properties of Self-Cascode Structures Composed by UTBB Transistors(2020) COSTA, F. J.; TREVISOLI, R.; Michelly De Souza; Rodrigo Doria© 2020 IEEE.The focus of this work is to perform an analysis of the thermal properties of the Self-Cascode (SC) structure composed by advanced UTBB SOI MOSFETs under a selected set of back gate biases, through 2D numerical simulations. In this work, it could be observed that the SC structure presents a 50 % lower thermal resistance in comparison with a single device with similar channel length. The application of a back gate bias of 2 V to the drain-sided device or -2 V to the source-sided devices of the SC has shown a decrease of 10-16 % in the thermal resistance.