Engenharia Elétrica
URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/21
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11 resultados
Resultados da Pesquisa
- Charge Pumping-Based Method for Traps Density Extraction in Junctionless Transistors(2021) FONTE, E. T.; TREVISOLI, R.; Rodrido Doria© 2021 IEEE.A study of Junctionless Transistors (JNTs) is presented in this work, with emphasis on verifying the extraction of the interface traps density using the charge pumping method. To the best of our knowledge, this is the first work to use this method in JNTs. The method was applied to both simulated and experimental data and has shown satisfactory results.
- Application of junctionless nanowire transistor in the self-cascode configuration to improve the analog performance(2012-09-02) Rodrido Doria; TREVISOLI, R. D.; Michelly De Souza; Marcelo Antonio PavanelloThe self-cascode (SC) configuration consists in a series association of two transistors with tied gates usually applied to improve the analog performance of MOS devices. This paper compares the analog parameters of single Junctionless transistors with the ones presented by self-cascode associations composed by two Junctionless devices with identical or different fin widths (symmetric and asymmetric, respectively). The transconductance to the drain current ratio, the Early voltage (VEA) and the intrinsic voltage gain (AV) have been evaluated for both single devices and SC structures. It has been shown that the SC configurations, specially the asymmetric ones, present a strong reduction of the drain conductance (gD) with respect to single devices, resulting in an increase of VEA and AV, which can be higher than 30 dB depending on the bias conditions. © The Electrochemical Society.
- Analytical model for potential in double-gate juntionless transistors(2013-09-06) CERDEIRA, A.; ESTRADA, M.; TREVISOLI, R. D.; Rodrido Doria; Michelly De Souza; Marcelo Antonio PavanelloAn analytical model to calculate the potential at the surface and at the center of silicon layer for long-channel Junctionless transistors is derived and explained the basic details. The analytical model is compared with the numerical solution of the fundamental equations showing the validity of the assumptions considered. © 2013 IEEE.
- The influence of the substrate bias in Junctionless nanowire transistors(2013-09-06) TREVISOLI, R. D..; Rodrido Doria; Michelly De Souza; Marcelo Antonio PavanelloThis work aims at analyzing the influence of the substrate bias in the operation of Junctionless Nanowire Transistors. The analysis is based on simulated and experimental data. The discussion about the substrate influence on the devices operation is also accomplished by modeled results. The threshold voltage and the maximum transconductance dependence on the substrate bias are the key parameters under analysis. © 2013 IEEE.
- Analysis of charges densities in multiple-gates SOI nMOS junctionless(2013-09-06) MARINIELLO, G.; CERDEIRA, A.; ESTRADA, M.; Rodrido Doria; TREVISOLI, R. D.; Michelly De Souza; Marcelo Antonio PavanelloThis paper aims to analyze the charges density in multiple gates junctionless devices with different dimensions The analysis of the charge densities was done at the center of the silicon film, at the sidewall and at the top interfaces between the silicon and the gate oxide, for devices with different fin width, height and gate oxide tickness. Based on this analisys, the occurrence of corner effects in Junctionless devices is investigated. © 2013 IEEE.
- Analog operation of junctionless nanowire transistors down to liquid helium temperature(2014-07-09) TREVISOLI, R.; Michelly De Souza; Rodrido Doria; KILCHYTSHA, V.; FLANDRE, D.; Marcelo Antonio PavanelloThe aim of this work is to analyze the analog operation of Junctionless Nanowire Transistors at temperatures down to liquid helium temperature. The analysis is performed in terms of the transconductance, open loop voltage gain and output conductance for experimental long channel devices. It is shown that the temperature reduction can affect significantly the analog performance of the devices. © 2014 IEEE.
- Effect of the temperature on on Junctionless Nanowire Transistors electrical parameters down to 4K(2014-10-29) TREVISOLI, R.; Michelly De Souza; Rodrido Doria; KILCHTYSKA, V.; FLANDRE, D.; Marcelo Antonio PavanelloThe aim of this work is to analyze the operation of Junctionless Nanowire Transistors at liquid helium temperature, focusing the operation at linear regime. The drain current, the transconductance, the low field mobility, subthreshold slope, the interface trap density and the channel resistance are the key parameters under analysis.
- Effective mobility analysis of n- and p-types SOI junctionless nanowire transistors(2014-10-29) Rodrido Doria; TREVISOLI, R.; Michelly De Souza; Marcelo Antonio PavanelloThis paper reports the behavior of the effective mobility of n- and p-type SOI Trigate Junctionless Nanowire Transistors with different doping concentrations and channel widths down to 20 nm-wide devices. It is shown that the mobility of extremely narrow devices can overcome the bulk silicon mobility independently of the device type. The increase in the maximum mobility observed in narrow devices seems to be more pronounced for heavier doped devices.
- Improved analog operation of junctionless nanowire transistors using back bias(2015-03-18) TREVISOLI, R.; Rodrido Doria; Michelly De Souza; Marcelo Antonio PavanelloThis work reports, for the first time, an analysis of substrate bias on the analog parameters of Junctionless Nanowire Transistors operating as single transistor amplifiers through experimental and simulated data. The study is performed in terms of output conductance, transconductance, open loop voltage gain and transconductance to the drain current ratio. It has been shown that the substrate bias can affect significantly the performance of junctionless devices, such that the positive back bias can reduce the output conductance and improve the voltage gain.
- Effective channel length in Junctionless Nanowire Transistors(2015-10-13) TREVISOLLI, R.; Rodrido Doria; Michelly De Souza; Marcelo Antonio PavanelloThe aim of this work is to analyze the influence of the lateral depletion induced by the gate towards the source/drain regions on the effective channel length of Junctionless Nanowire Transistors. The effective channel length increase at the subthreshold regime is analyzed by means of simulations together with experimental results, showing that the JNT can be significantly longer than the gate length.