Engenharia Elétrica
URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/21
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6 resultados
Resultados da Pesquisa
- The roles of the electric field and the density of carriers in the improved output conductance of junctionless nanowire transistors(2011-01-05) Rodrigo Doria; Marcelo Antonio Pavanello; TREVISOLI, R. D.; Michelly De Souza; LEE, C. W.; FERAIN, I.; DEHDASHTI AKHAVAN, N.; YAN, R.; RAZAVI, P.; YU, R.; KRANTI, A.; COLINGE, J. P.This paper evaluates the roles of the electric field (E) and the density of carries (n) in the drain conductance of Junctionless Nanowire Transistors (JNTs). The behavior of E and n presented by JNTs with the variation of the gate and the drain voltages has been compared to the one presented by Inversion Mode (M) Trigate devices of similar dimensions. It has been shown that the lower drain output conductance exhibited by Junctionless transistors with respect to the IM ones is correlated not only to the differences in the mobility and its degradation but also to the electric field, the density of carries and the first order derivative of these variables with respect the drain voltage. ©The Electrochemical Society.
- Impact of the series resistance in the I-V characteristics of nMOS junctionless nanowire transistors(2011-09-02) Rodrigo Doria; TREVISOLI, D. T.; Marcelo Antonio PavanelloThe series resistance (Rs) of Junctionless Nanowire Transistors (JNTs) with different doping concentrations was extracted from 473 K down to 100 K. The source/drain parasitic resistance presented by JNTs was compared to the one presented by classical inversion mode (IM) triple gate devices and the impact of the series resistance on the drain current of the devices was evaluated. The R S analysis was carried out through experimental results and devices tridimensional numerical simulations. According to the study, R S presents opposite behavior with the temperature variation in EVI triple transistors and JNTs. In the latter, a reduction on R S is noted with the temperature increase, whereas a resistance decrease is obtained with the temperature lowering in IM devices. The parasitic resistance in JNTs affects the drain current in such a way that there may not be a Zero Temperature Coefficient (ZTC) operation point. © The Electrochemical Society.
- Temperature and back-gate bias influence on the operation of lateral SOI PIN photodiodes(2014-09-05) NOVO, C.; GIACOMINI, R. DORIA, R.; AFZALIAN, A.; FLANDRE. D.Temperature and back-gate bias influence on the operation of lateral SOI PIN photodiodes. 2014 29th Symposium on Microelectronics Technology and Devices: Chip in Aracaju, SBMicro 2014,; Renato Giacomini; Rodrigo Doria; AFZALIAN, A.; FLANDRE. D.© 2014 IEEE.This paper presents a study of back-gate bias and temperature influence on the operation of lateral SOI PIN photodiodes. Experimental results showed that the operation mode of the photodiodes is affected by back-gate bias, modifying the photogenerated current, which has a strong influence on the illuminated to dark ratio, as well as, on the quantum efficiency. At lower temperatures, the results showed that the quantum efficiency can be improved by biasing the device in inversion mode, while at higher temperatures, the accumulation mode showed a higher illuminated to dark ratio.
- Physical insights on the dynamic response of junctionless nanowire transistors(2016-11-02) Rodrigo Doria; TREVISOLI, R.; Michelly De Souza; Marcelo Antonio PavanelloThe aim of this work is to present, for the first time, an analysis of the maximum oscillation frequency (fmax) presented by Junctionless Nanowire Transistors (JNTs) as well as its impact and the carriers transit time on the minimum switching time of these devices. It has been observed that despite presenting lower fmax than inversion mode devices, fmax of JNTs is benefited by its lower capacitances along a large interval in its operation range. Also, it has been shown that the transit time can significantly influence on the minimum switching time of long devices, since it can be larger than the minimum oscillation time, what does not occur in shorter JNTs.
- Experimental comparative analysis between junctionless and inversion mode nanowire transistors down to 10 nm-long channel lengths(2018-10-18) Rodrigo Doria; TREVISOLI, R.; Michelly De Souza; Marcelo Antonio Pavanello; VINET, M.; CASSE, M.; FAYNOT, O.This paper aims at presenting, for the first time, an experimental comparative analysis between the main electrical parameters of Junctionless (JNT) and inversion mode nanowire (IM) transistors fabricated in SOI technology down to channel length of 10 nm. The analysis has shown that JNTs present larger immunity to SCEs with respect to IM nanowires of similar dimensions. However, JNTs have shown poorer Ion than IM devices, which could be compensated through the application of multifin JNTs, at cost of increasing area consumption.
- Compact Analytical Model for Trap-Related Low Frequency Noise in Junctionless Transistors(2019-09-26) TREVISOLI, R.; Rodrigo Doria; BARRAUD, S.; Marcelo Antonio PavanelloThe aim of this work is to propose a compact analytical model for the Low Frequency Noise (LFN) in Junctionless Nanowire Transistors (JNTs). Since JNTs work differently from inversion mode transistors, the noise is also expected to behave differently. To the best of our knowledge, no analytical models have been presented for LFN in these devices. The proposed model is validated through numerical simulations. Experimental results are also used to demonstrate its applicability.