Engenharia Elétrica
URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/21
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20 resultados
Resultados da Pesquisa
- Junctionless nanowire transistors effective channel length extraction through capacitance characteristics(2023-10-05) SILVA, E. M.; TREVISOLI, R.; Rodrigo Doria© 2023 Elsevier LtdThis work aims to extract the effective channel length (LEFF) of Junctionless Nanowire Transistors (JNT) through the maximum gate capacitance of the devices. The LEFF extraction has been done by extrapolating the maximum gate capacitance as a function of the devices’ channel length (LMASK) and has shown that LEFF is around 10–15 nm longer than LMASK for devices of different channel doping concentrations.
- Ultra-Low-Power Diodes Composed by SOI UTBB Transistors(2022-07-04) COSTA, F. J.; TREVISOLI, R.; Rodrigo Doria© 2022 IEEE.The main objective of this work is to present an analysis of the performance of Ultra-Thin-Body and Buried Oxide transistors working as Ultra-Low-Power diodes. The implementation of different ground planes and substrate biases are analyzed. It is shown a reduced leakage current and increased ratio between the on and off-state currents for the Ultra-Low-Power diode with the N-substrate biased at -2V. However, this condition results in increased threshold voltage. The ground planes do not provoke a significant change in the leakage current, but a noticeable variation can be observed in the ratio between the on and off-state currents due to the higher threshold voltage in relation to the system without ground plane.
- Junctionless Nanowire Transistor for Analog Applications: Cascode Current Mirror Configuration(2022-08-05) SHIBUTANI, A. B.; TREVISOLI, R.; Rodrigo Doria© 2022 IEEE.In this paper, a cascode current mirror compounded by junctionless nanowire transistors is analyzed for the first time. Thus, the performance and the mirroring precision of the configuration were investigated considering the internal circuit feedback and the high output resistance. On this basis, symmetrical and asymmetrical configurations were examined to comprehend the junctionless nanowire transistor behavior as a current source.
- Standard MOS Diodes Composed by SOI UTBB Transistors(2022-08-05) COSTA, F. J.; TREVISOLI, R.; CAPOVILLA, C. E.; Rodrigo Doria© 2022 IEEE.The main objective of this work is to present an analysis of the performance of UTBB SOI transistors working as standard diodes, where the implementation of ground planes and substrate bias are analyzed. It is shown a reduced leakage current and increased ratio between the on and off-state currents with the substrate bias at -2 V and with a P-type GP implemented. However, both conditions result in increased threshold voltage.
- SOI UTBB Capacitive Cross-Coupling Effects in Ultimate Technological Nodes(2022-03-01) COSTA, F. J.; TREVISOLI, R.; Rodrigo Doria© 2022 IEEE.The main objective of this work is to carry out an analysis of the effects of cross-coupling in a system composed of SOI UTBB MOSFETs in ultimate integration nodes through numerical simulations, validated with experimental data from literature. In this analysis, it could be observed that two devices located on the channel length direction provoke a reduced cross-coupling on each other. For devices located at distances below 50 nm, a capacitive parasitic coupling between the devices can be observed along with the thermal coupling effect.
- Variability Modeling in Triple-Gate Junctionless Nanowire Transistors(2022-01-05) TREVISOLI, R.; Marcelo Antonio Pavanello; Rodrigo Doria; CAPOVILLA, C.E.; BARRAUD, S.; Michelly De SouzaIEEEThis work aims at proposing an analytical model for the variability of the threshold voltage and drain current in junctionless nanowire transistors. The model is continuous in all operation regions and has been validated through Monte Carlo simulations using a physically based drain current model and 3-D numerical simulations. A discussion about the influences of each variability source based on the proposed model is carried out. Finally, the modeled results are compared to the experimental data for a fully physical validation.
- NBTI Dependence on Temperature in Junctionless Nanowire Transistors(2021-07-27) GRAZIANO, N.; TREVISOLI, R.; Rodrigo, Doria©2021 IEEE.This paper discusses the nature of degradation by NBTI effect in pMOS junctionless devices when varying the temperature. The results were obtained through simulations validated to experimental data. Devices with different dimensions and doping, have been subjected to a temperature range that varies between 270 and 380 K. The simulations were performed for different values of VGT and as a result it is possible to observe that when increasing temperature up to 340 K, the threshold voltage variation due to NBTI is also increased. However, for larger temperatures the NBTI effect seems to stabilize or even reduce.
- Interface traps density extraction through transient measurements in junctionless transistors(2022-08-05) TEICEIRA DA FONTE, E.; TREVISOLI, R.; BARRAUD S.; Rodrigo Doria© 2022 Elsevier LtdThis paper presents an extraction method for the interface traps density on Junctionless Transistors (JNTs) using an adapted charge pumping technique. To the best of our knowledge, this is the first work to apply this method in JNTs. Initially, it was stated through numerical simulations that a transient current, which increases with the trap density, is observed in the devices when the charge pumping method is applied. Then, a measurement setup was proposed to extract the pumping current resultant from a gate pulse and a mathematical expression was proposed to extract the density of trapped charges in the Oxide/Silicon interface (Nit). Aiming to demonstrate the method applicability for determining the JNTs interface quality, it was applied to simulations considering different trap densities as well as to experimental data of Junctionless Nanowire Transistors. It was observed that the method accuracy increases for larger trap densities and presents agreement to theoretical data for Nit > 1 × 1011 cm−2.
- Cross-coupling effects in common-source current mirrors composed by UTBB transistors(2022) JOSÉ DA COSTA, F.; TREVISOLI, R.; Rodrigo Doria© 2022 Elsevier LtdThis work performs an analysis of the cross-coupling effects influence on the performance of current mirrors composed by advanced UTBB SOI MOSFETs through 3D numerical simulations validated to experimental data of single devices. It is shown the presence of a capacitive coupling acting in the system, which can be demonstrated through the threshold voltage reduction at small distances between devices. Additionally, the temperature rise in the system due to the thermal coupling provokes a decrease in the input current as the devices become closer to each other. This is responsible for an increase of 3 % on ID2/ID1 ratio when the devices are biased at the same time and when the distance between them is lowered to 100 nm.
- Modeling Schottky Diode Rectifiers Considering the Reverse Conduction for RF Wireless Power Transfer(2022-03-01) TREVISOLI, R.; DA PAZ, H. P.; DA SILVA, V. S.; Rodrigo Doria; CASELLA, I. R. S.; CAPOVILLA, C. E.© 2004-2012 IEEE.The aim of this work is to model Schottky diodes series rectifier for application in Radio Frequency Energy Harvesting (RFEH). A time-domain approach is proposed, including the reverse conduction of the diodes, which can significantly degrade the Power Conversion Efficiency (PCE) as the diode input power increases. The influences of the load, temperature, matching network and choke inductor have also been considered. The representativeness of the model was validated by means of computer simulations and experimental results.